• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.2
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• pp.89-93
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• 2017

GaN single crystals were grown by controlling of various processing parameters such as growing temperature, V/III ratio and growing rate. We optimized thickness of bulk GaN single crystal by analyzing defect of surface and inside of the GaN single crystal for application to high brightness and power device. 2-inch bulk GaN single crystals were grown by HVPE (hydride vapor phase epitaxy) on sapphire and their thickness was 0.3~7.0 mm. Crystal structure of the grown bulk GaN was analyzed by XRD (X-ray diffraction). The surface characteristics of the grown bulk GaN were observed by OM (optical microscope) and SEM (scanning electron microscopy) with measuring EPD (etch pits density) of the GaN crystals.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.33 no.4
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• pp.153-157
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• 2023

In order to manufacture a semiconductor circuit, etching, cleaning, and deposition processes are repeated. During these processes, the inside of the processing chamber is exposed to corrosive plasma. Therefore, the coating of the inner wall of the semiconductor equipment with a plasma-resistant material has been attempted to minimize the etching of the coating and particle contaminant generation. In this study, we mixed AlF₃ powder with the solid-state reacted yttrium oxyfluoride (YOF) in order to increase plasma-etching resistance of the plasma spray coated YOF layer. Effects of the mixing ratio of AlF₃ with YOF powder on crystal structure, microstructure and chemical composition were investigated using XRD and FE-SEM. The plasma-etching ratios of the plasma-spray coated layers were calculated and correlation with AlF₃ mixing ratio was analyzed.

• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.347-347
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• 2009

결정질 태양전지의 공정에 있어서 호모지니어스(homogeneous)한 구조보다 향상된 변환효율을 얻기 위해 선택적 도핑 방법에 관한 연구가 활발하다. 선택적 도핑 방법이란 에미터(emitter) 층을 $n^{++}$ 영역과 $n^+$ 영역으로 나누어 향상된 전류밀도와 개방전압을 얻기 위한 방법이다. 본 연구에서 제시된 RIE 에치-백 구조는 다수의 선택적 도핑 방법 중 하나이다. 기존의 에치-백 구조는 전면 전극 형성 후 RIE 공정을 수행하기 때문에 전면 전극이 손상되고 RIE 데미지(damage)가 발생되는 문제점이 있었다. 그러나 본 연구에서 제시된 구조는 기존의 에치-백 구조와 달리 RIE 에칭 후 발생된 데미지를 제거하는 추가적인 공정인 질산 패시베이션(nitric acid passivation)이 수행되었다. 또한 본 연구에서 새롭게 제시된 블라킹 마스크 페이스트(blocking mask paste)는 기존의 에치-백 구조에서 발생된 전극 손상 문제를 해결해 주고 있다. 이러한 결과로 호모지니어스 구조보다 향상된 전류밀도 (35.77 mA/$cm^2$), 개방전압 (625 mV), FF (78.01%), 변환효율 (17.43%)를 얻었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.297-297
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• 2013

최근 각종 폴리머 및 강판과 같은 유연소재의 수요 증가로 인해 유연소재 표면의 전처리, 증착 및 기능성 부여를 위한 이온빔 또는 플라즈마 표면처리 기술이 세계적으로 활발히 연구개발 되고 있으며, 유연소재 표면처리 공정의 고속화 및 대면적화 기술이 요구되고 있다. 유연소재의 고속 및 대면적 표면처리 기술개발을 위해서는 Roll-to-Roll 공정에 적용 가능한 광폭 선형이온소스 기술 개발이 필요하다. 본 연구에서는 1.55 m급 광폭 Anode Layer 선형이온소스를 개발하였으며, 이온빔 인출 균일도 및 에너지 분포 특성을 평가하였다. 특히, 본 선형이온 소스 개발 시 시뮬레이션 연구를 통해 이온소소의 이온 인출 특성 및 내구성 향상을 위한 최적 구조를 설계하였다. 본 연구에서 개발한 선형이온소스는 최대 5 kV의 방전 전압 조건에서 평균 1.5 keV의 이온에너지를 가지는 Ar 이온빔이 1.55 m 폭에서 약 4.2%의 균일도를 보였다. 표면 처리 성능 평가시(Si wafer 기준) 소스와 기판과 거리 100 mm에서 에칭율은 15 nm/s였고, 이는 다른 표면처리 이온소스 대비 높은 효율을 나타냄을 확인할 수 있었다. 또한 4시간 이상 운전시에도 안정적인 인출 빔 전류 밀도를 확인하였으며, 소스 내부의 효율적인 냉각 구조로 인한 열손상은 발견되지 않았다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.67-72
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• 1989

Room Temperature Plasma Nitridation of silicon was investigated as a new LOCOS (local oxidation of silicon) process in order to reduce the bird's beak length. In $N_2$ plasma formed by 100kHz, 400W AC power, a thin silicon nitride film (<100${\AA}$) was uniformly grown on a silicon substrate. SEM studies showed that the nitride layer formed by this method can effectively protect the silicon from oxidation and reduce the bird's beak length to $0.2{mu}m$ when 4000${\AA}$ field oxide is grown. This is a considerable improvement comparing with 0.7${mu}m,$ the bird's beak, for the conventional LOCOS process using a thick LPCVD nitride. No appreciable crystalline defect could be found around the bird's beak with SEM cross-section afrer Secco etch. Leakage current tests were carried out on the $N^+/P^-$ well and $P^+/N^-$ well diodes formed by this new LOCOS process. The electrical tests indicate that this new process has electrical properties similar or superior to those of the conventional LOCOS process.

• Clean Technology
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• v.27 no.3
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• pp.240-246
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• 2021

The waste etching solution for chip on film (COF) contained about 3.5% copper, and it was recovered through cementation using iron samples. The effect of cementation with plate, chip, and powder iron samples was investigated. The molar ratio (m/r) of iron to copper was used as a variable in order to increase the recovery rate of copper. As the molar ratio increased, the copper content in the solution rapidly decreased at the beginning of the cementation reaction. Before and after the reaction, the copper content of the solution was determined by Inductively Coupled Plasma (ICP) using copper concentration according to time. After cementation at room temperature for 1 hour, the recovery rate of copper had increased the most in the iron powder sample, having the largest specific surface area of the samples, followed by the chip and plate samples. The recovered copper powder was characterized for its crystalline phase, morphology, and elemental composition by X-ray diffraction (XRD), scanning electron microscopy (SEM), and Energy-dispersive X-ray spectroscopy (EDS), respectively. Copper and unreacted iron were present together in the iron powder samples. The optimum condition for recovering copper was obtained using iron chips with a molar ratio of iron to copper of 4 giving a recovery rate of about 98.4%.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.31 no.6
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• pp.276-281
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• 2021

In order to manufacture a semiconductor circuit, etching, cleaning, and deposition processes are repeated. During these processes, the inside of the processing chamber is exposed to corrosive plasma. Therefore, the coating of the inner wall of the semiconductor equipment with a plasma-resistant material has been attempted to minimize the etching of the coating and particle contaminant generation. In this study, we synthesized yttrium oxyfluoride (YOF) powder by a solid-state reaction using Y₂O₃ and YF₃ as raw materials. Mixing ratio of the Y₂O₃ and YF₃ was varied from 1.0:1.0 to 1.0:1.6. Effects of the mixing ratio on crystal structure and microstructure of the synthesized YOF powder were investigated using XRD and FE-SEM. The synthesized YOF powder was successfully applied to plasma spray coating process on Al substrate.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.98-104
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• 2023

The feasibility of an efficient process proposed for Cu-Cu flip-chip bonding was evaluated by forming a porous Cu layer on Cu pillar and conducting thermo-compression sinter-bonding after the infiltration of a reducing agent. The porous Cu layers on Cu pillars were manufactured through a three-step process of Zn plating-heat treatment-Zn selective etching. The average thickness of the formed porous Cu layer was approximately 2.3 ㎛. The flip-chip bonding was accomplished after infiltrating reducing solvent into porous Cu layer and pre-heating, and the layers were finally conducted into sintered joints through thermo-compression. With reduction behavior of Cu oxides and suppression of additional oxidation by the solvent, the porous Cu layer densified to thickness of approximately 1.1 ㎛ during the thermo-compression, and the Cu-Cu flip-chip bonding was eventually completed. As a result, a shear strength of approximately 11.2 MPa could be achieved after the bonding for 5 min under a pressure of 10 MPa at 300 ℃ in air. Because that was a result of partial bonding by only about 50% of the pillars, it was anticipated that a shear strength of 20 MPa or more could easily be obtained if all the pillars were induced to bond through process optimization.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.111-111
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• 2008

태양전지는 태양에너지를 직접 전기에너지로 변환시켜주는 광전 소자로서 구조적으로 단순하고 제조 공정도 비교적 간단하지만, 실용화를 위해서는 비용적인 측면이 많은 걸림돌이 되고 있다. 기존의 실리콘 태양전지는 낮은 광흡수율, 고비용임에도 불구하고 가장 많이 활용되고 있는 태양전지 기술이다. 그러나 태양전지의 경제성 향상과 실용화를 위해서는 기존의 실리콘 태양전지 보다 고효율 및 고신뢰도의 박막형 태양전지의 개발이 필요하다. 박막헝 태양전지의 재료로는 비정질 실리콘, 다결정 실리콘. CIGS, CdTe 등이 있다. 그 중에서도 박막형 태양전지에 광흡수층 물질로는 밴드갭 에너지 (l.4eV 부근), 변환 효율, 경제성 등을 고려했을 때 II-VI족 화합물인 CdTe가 가장 적합한 것으로 각광받고 있다. 하지만 아직까지 실리콘 태양전지에 비해 효율이 많이 떨어지는 단점을 가지고 있기 때문에 효율을 더 끌어올리기 위한 연구가 활발히 진행되고 있는 실정이다. 또한 CMP(chemical mechanical polishing) 공정은 반도체 박막 분야뿐만 아니라 물리, 화학 반응의 기초 연구에도 널리 응용이 되는 기술로써, 시료와 연마 패드 사이의 회전마찰에 의한 기계적 연마와 연마제 (abrasive) 에 의한 화학적 에칭으로 박막 표면을 평탄화하는 기술이다. 본 연구에서는 sputtering 법에 의해 증착된 CdTe 박막에 CMP 공정을 적용하여 표면 특성을 개선한 뒤 태양전지 변환 효율과 직접적인 연관성을 가지고 있는 표면 및 광특성의 변화를 CMP 공정 전과 후로 비교하였다. 표면의 변화를 관찰하기 위해서 AFM(atomic forced microscope) 과 SEM(scanning electron microscopy) 을 이용하였으며, 광특성의 비교를 위해서 흡수율과 PL특성을 측정하였다.