• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.55-60
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• 2020

The PERC photovoltaic (PV) modules installed in PV power plant are still reports potential-induced degradation (PID) degradation due to high voltage potential differences. This is because Na+ ions in the cover glass of PV modules go through the encapsulant (EVA) and transferred to the surface of solar cells. As positive charges are accumulated at the ARC (SiOx/SiNx) interface where many defects are distributed, shunt-resistance (Rsh) is reduced. As a result, the leakage current is increased, and decrease in solar cell's power output. In this study, to prevent of this phenomenon, a Moth-eye nanostructure was deposited on the rear surface of an optical film using Nano-Imprint Lithography method, and a solar mini-module was constructed by inserting it between the cover glass and the EVA. To analyze the PID phenomenon, a cell-level PID acceleration test based on IEC 62804-1 standard was conducted. Also analyzed power output (Pmax), efficiency, and shunt resistance through Light I-V and Dark I-V. As a result, conventional solar cells were decreased by 6.3% from the initial efficiency of 19.76%, but the improved solar cells with the Moth-eye nanostructured optical film only decreased 0.6%, thereby preventing the PID phenomenon. As of Moth-eye nanostructured optical film, the transmittance was improved by 4%, and the solar module output was improved by 2.5%.

• Korean Journal of Optics and Photonics
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• v.33 no.4
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• pp.137-145
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• 2022

A directional coupler device, one of the fundamental components of photonic integrated circuits, distributes optical power by evanescent field coupling between two adjacent optical waveguides. In this paper, the design process for manufacturing a directional coupler device is reviewed, and the accuracy of the design results, as seen from the characteristics of the actual fabricated device, is confirmed. When designing a directional coupler device through a two-dimensional (2D) beam-propagation-method (BPM) simulation, an optical structure is converted to a two-dimensional planar structure through the effective index method. After fabricating the directional coupler device array, the characteristics are measured. To supplement the 2D-BPM results that are different from the experimental results, a 3D-BPM simulation is performed. Although 3D-BPM simulation requires more computational resources, the simulation result is closer to the experimental results. Furthermore, the waveguide core refractive index used in 3D-BPM is adjusted to produce a simulation result consistent with the experimental results. The proposed design procedure enables accurate design of directional coupler devices, predicting the experimental results based on 3D-BPM.

• Journal of Life Science
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• v.33 no.9
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• pp.730-735
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• 2023

In the past decade, numerous studies have been carried out to quantify aging with the help of artificial intelligence. Using DNA methylation data, various models have been developed; these are commonly called epigenetic clocks. Epigenetic age acceleration is usually associated with disease conditions. Schizophrenia is a mental illness associated with severe mental and physical stress. This disease leads to high mortality and morbidity rates in young people compared with other psychological disorders. In the past, the research community considered this disease to be related to the accelerated aging hypothesis. In the current study, we wanted to investigate the epigenetic age acceleration changes in schizophrenia patients to obtain epigenetic insights into the disease. To measure the epigenetic age acceleration, we used two different DNA methylation clock models, namely, Horvath clock and Epi clock, as these are pan-tissue models. We utilized 450k array data compatible with both clocks. We found a slower epigenetic acceleration in the patients' samples when we used the Epi clock. We further analyzed the differentially methylated CpG sites between the control and cases and performed pathway enrichment analysis. We found that most of the CpGs are involved in neuronal processes.

• Journal of Biomedical Engineering Research
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• v.44 no.6
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• pp.404-413
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• 2023

In this research, we studied the development of a SUS304 microneedle array based on microfabrication technology and the applicability of Parylene-C thin film, a medical polymer material. First of all, four materials commonly used in the field of medical engineering (SUS304, Ti, PMMA, and PEEK) were selected and a 5 ㎛ Parylene-C thin film was deposited. The applicability of Parylene-C coating to each material was confirmed through SEM analysis, contact angle measurement, surface roughness(Ra) measurement, and adhesion test according to ASTM standards for each specimen. Parylene-C thin film was deposited based on chemical vapor deposition (CVD), and a 5 ㎛ Parylene-C deposition process was established through trial and error. Through characteristic experiments to confirm the applicability of Parylene-C, SUS304 material, which is the easiest to apply Parylene-C coating without pretreatment was selected to develop a microneedle array based on CNC micromachining technology. The CNC micromachining process was divided into a total of 5 steps, and a microneedle array consisting of 19 needles with an inner diameter of 200 ㎛, an outer diameter of 400 ㎛, and a height of 1.4 mm was designed and manufactured. Finally, a 5 ㎛ Parylene-C coated microneedle array was developed, which presented future research directions in the field of microneedle-based drug delivery systems.

• Journal of the Korean Electrochemical Society
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• v.23 no.2
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• pp.25-38
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• 2020

Photoelectrochemical water splitting has been considered as the most promising technology for generating hydrogen energy. Transition metal dichalcogenide (TMD) compounds have currently attracted tremendous attention due to their outstanding ability towards the catalytic water-splitting hydrogen evolution reaction (HER). Herein, we report the synthesis method of various transition metal dichalcogenide including MoS₂, MoSe₂, WS₂, and WSe₂ nanosheets as excellent catalysts for solar-driven photoelectrochemical (PEC) hydrogen evolution. Photocathodes were fabricated by growing the nanosheets directly onto Si nanowire (NW) arrays, with a thickness of 20 nm. The metal ion layers were formed by soaking the metal chloride ethanol solution and subsequent sulfurization or selenization produced the transition metal chalcogenide. They all exhibit excellent PEC performance in 0.5 M H₂SO₄; the photocurrent reaches to 20 mA cm^-2 (at 0 V vs. RHE) and the onset potential is 0.2 V under AM1.5 condition. The quantum efficiency of hydrogen generation is avg. 90%. The stability of MoS₂ and MoSe₂ is 90% for 3h, which is higher than that (80%) of WS₂ and WSe₂. Detailed structure analysis using X-ray photoelectron spectroscopy for before/after HER reveals that the Si-WS₂ and Si-WSe₂ experience more oxidation of Si NWs than Si-MoS₂ and Si-MoSe₂. This can be explained by the less protection of Si NW surface by their flake shape morphology. The high catalytic activity of TMDs should be the main cause of this enhanced PEC performance, promising efficient water-splitting Si-based PEC cells.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.