• Title/Summary/Keyword: 어드레스 오방전

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Cost Effective Plasma Display Panel TV Driving system with an address misfiring compensation circuit (어드레스 오방전 보상 저가형 플라즈마 디스플레이 패널 TV 구동 시스템)

  • Yi, Kang Hyun;Lee, Dae Sik
    • Journal of Korea Society of Industrial Information Systems
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    • v.18 no.3
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    • pp.1-8
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    • 2013
  • Plasma display panel (PDP) televisions are facing to have a new chance to receive attention along with a boom in 3-D software and contents because PDP can provide the comfortable and realistic 3-D images. The PDP has three driving circuit boards such as X, Y and addressing boards. Cost effective driving waveform has already been reported to decrease the number of driving circuit board. Half bridge based sustaining driver can remove a sustaining driver in the X board. However, the biasing circuit in the X driving boards cannot be reduced because there are some drawbacks such as unstable gas discharge condition and unreliability of an address driver IC. In this paper, the half bridge based sustaining driver is considered and a simple address driver is proposed to remove one driving board, X driving board. The stable gas discharge condition, reliability of the address driver IC and the low cost can be obtained by the proposed circuit.

Study on the Address Discharge Characteristics for the Improvement of the Mis-firing Problem in AC PDP (AC PDP의 오방전 개선을 위한 어드레스 방전 특성 연구)

  • Jeon, Won-Jae;Kim, Dong-Hun;Lee, Seok-Hyun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.6
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    • pp.1151-1156
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    • 2009
  • Unstable sustain discharges can occur at the bottom cells of the panel at high temperature. To solve this problem, the wall charge variation during an address period was investigated. A test panel of 7.5 inch XGA level was used and one green cell was measured. In order to realize operating condition equal to that of the bottom cells of 50 inch panel, the addressing stress pulses are applied. It seems that the resultant wall charge loss during address period increased with increase of stress time, temperature, pressure and Xe %. Wall charge loss increases with potential difference between scan electrode and address electrode, therefore wall charge loss can be minimized by the increase of scan voltage during address period.