• Journal of KIISE:Information Networking
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• v.32 no.3
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• pp.427-432
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• 2005

Packet arrival rates in internet routers have been dramatically increased due to the advance of link technologies, and hence wire-speed packet processing in Internet routers becomes more challenging. As IP address lookup is one of the most essential functions for packet processing, algorithm and architectures for efficient IP address lookup have been widely studied. In this paper, we Propose an efficient I address lookup architecture which shows yeW good Performance in search speed while requires a single small-size memory The proposed architecture is based on multi-way tree structure which performs comparisons of multiple prefixes by one memory access. Performance evaluation results show that the proposed architecture requires a 280kByte SRAM to store about 40000 prefix samples and an address lookup is achieved by 5.9 memory accesses in average.

• Korean Journal of Optics and Photonics
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• v.10 no.1
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• pp.32-39
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• 1999

In this paper, we made CGH patterns that had continuous amplitude distribution binary coded patterns with two different methods, and analyzed those patterns by using LCSLM (liquid crystal spatial light modulator). The error diffusion algorithm and direct quantization method were used as the binarization methods. The parameters of overall average brightness, mean square error, and diffraction efficiency were used in the comparison of reconstruction characteristics. The LCSLM which we used in this experiment was a binary reflective ferroelectric liquid crystal spatial light modulator addressed electrically with 256$\times$256 pixels, 87% fill factor and 15$\mu$m pixel pitch.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.51-60
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• 1999

For an effective phase-multiplexing in holographic memory system, four types of phase code used as reference beam are generated. In case of $32 {\times} 32$ address beam, a phase error with 0%, 5%, 10% 15%, 20%, and 25% error rate, is purposely added to the real phase values in order to consider the practical SLM's nonlinear characteristics of phase modulation in computer simulation, cross talks and SNRs are comparatively analysed for these phase-codes by the auto and cross-correlation. Pseudo-Random(PSR) Phase Code has the lowest cross-correlation mean value of 0.067 among four types of Phase Code, which means the SNR of the PSR is higher than other Phase Codes. Also, the standard deviation of the PSR phase code indicating the degree of recalled data degradation is the lowest value of 0.0113.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• 전자공학회논문지 IE
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• v.44 no.3
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• pp.23-34
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• 2007

For an effective phase multiplexing in a volume holographic system, four types of phase code, pseudo random code(PSC), Hadamard matrix(HAM), pure random code(PRC), equivalent random code(ERC), used as reference beams are generated. In case of $32{\times}32$ address beam, a phase error with 0%, 5%, 10%, 15%, 20%, and 25% error rate, is purposely added to the real phase values in order to consider the practical SLM's nonlinear characteristics of phase modulation in computer simulation. Crosstalks and SNRs(signal-to-ratio) are comparatively analyzed for these phase codes by the auto-correlation and cross-correlation. PSC has the lowest cross-correlation mean value of 0.067 among four types of phase code, which means the SNR of the pseudo random phase code is higher than other phase codes. Also, the standard deviation of the pseudo random phase code indicating the degree of recalled data degradation is the lowest value of 0.0113. In order to analyze the affect by variation of pixel size, simulation is carried out by same method for the case of $32{\times}32$, $64{\times}64$, $128{\times}128$, $256{\times}256$ address beams.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.1-7
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• 2010

In this paper, we suggested a sensing method of PoRAM with the multilevel cell When a specific voltage is applied between top and bottom electrodes of PoRAM unit cell, we can distinguish cell states by changing resistance values of the cell. Especially, we can use the PoRAM as the multilevel cell due to have four stable resistance values per cell. Therefore, we proposed an address decoding method, sense amplifier and control signal for sensing of a multilevel cell. The sense amplifier is designed based on a current comparator that compared a cell current the cell with a reference current, and have a low input impedance for a amplification of the current. The proposed circuit was designed in a $0.13{\mu}m$ CMOS technology, we verified to sense each data "00", "01", "10", "10" by four states of a cell current.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.