• Journal of the Korean GEO-environmental Society
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• v.15 no.10
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• pp.29-34
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• 2014

In order to examine strength properties depended on climate changes of solidified soil amended by porosity silica which enhance harms of cement, this study conducts a wetting and drying repetition test and then, attempts to verify strength properties before and after solidified soil gets environmental influence. Test pieces for the unconfined compression test changed the mixing ratio of solidified soil compared to mixed soil weigh to 5 %, 10 % and 15 %. For each step, it was created by mixing 0.5 %, 1.0 % and 1.5 % of wood chips, and curing period for 7, 14, and 28 days. Then, the wetting and drying repetition process was repeated 0, 3, 6, and 12 cycles to analyze mechanical properties. To also evaluate changes of relative dynamic elastic modulus before and after the wetting and drying, dynamic elastic modulus tests were conducted when each cycle was completed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

• Proceedings of the Korea Concrete Institute Conference
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• 2008.11a
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• pp.677-680
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• 2008

The autogenous shrinkage of HPC is important in that it can lead the early cracks in concrete structures. The purpose of the present study is to explore the autogenous shrinkage of HPC with cellulose fiber and expansive additive and to derive a realistic equation to estimate the autogenous shrinkage model of that. For this purpose, comprehensive experimental program has been set up to observe the autogenous shrinkage for various test series. Major test variables were the quantity of expansive additive and cellulose fiber. Water-cement ratio is fixed with 13%. The autogenous shrinkage of HPC is found to decrease with increasing expansive additive and cellulose fiber. A prediction equation to estimate the autogenous shrinkage of HPC was derived and proposed in this study. The proposed equation shows reasonably good correlation with test data on autogenous shrinkage of HPC.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.100-105
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• 2009

A watermarking for copyright protection of digital contents for broadcasting have to be made for a real-time system. In this paper, we propose a real-time video watermarking chip and system which is hardware based watermark embedding system of SD/HD video. Our chip is implemented by FPGA which is STRATIX device from ALTERA, and our system is implemented by GS1560A and GS1532 devices from GENNUM for HD/SD video signal processing. There was little visual artifact due to watermarking in subjective quality evaluation between the original video and the watermarked one. Embedded watermark was all extracted after a robustness test called natural video attacks such as A/D conversion and MPEG compression. Our implemented watermarking hardware system can be useful in movie production and broadcasting companies that requires real-time based copyright protection system.

• Journal of Broadcast Engineering
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• v.25 no.2
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• pp.200-207
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• 2020

Recently, deep neural networks such as CNN are showing excellent performance in various fields such as image classification, object recognition, visual quality enhancement, etc. However, as the model size and computational complexity of deep learning models for most applications increases, it is hard to apply neural networks to IoT and mobile environments. Therefore, neural network compression algorithms for reducing the model size while keeping the performance have been being studied. In this paper, we apply few compression methods to CNN models and evaluate their performances in the embedded environment. For evaluate the performance, the classification performance and inference time of the original CNN models and the compressed CNN models on the image inputted by the camera are evaluated in the embedded board equipped with QCS605, which is a customized AI chip. In this paper, a few CNN models of MobileNetV2, ResNet50, and VGG-16 are compressed by applying the methods of pruning and matrix decomposition. The experimental results show that the compressed models give not only the model size reduction of 1.3~11.2 times at a classification performance loss of less than 2% compared to the original model, but also the inference time reduction of 1.2~2.21 times, and the memory reduction of 1.2~3.8 times in the embedded board.

• Korean Journal of Agricultural Science
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• v.30 no.1
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• pp.76-88
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• 2003

This study exploits the robot system which is necessary in gene study, bio-technology industry. As well, it can achieve the job of DNA chip manufacturing whose use rate has been increased recently. The robot consists of DNA spotting device for spotting DNA on the silylated slide and well plate, bed for fixing well-plate, washing & drying device of washing and drying the pin part of DNA spotting device, distillation-water vessel, and discharge vessel of wash water. We made the term of sticking DNA to the pin on well plate to be 15 seconds. The spot size of DNA was set to be 0.28 mm on the average by bringing the slide into contact with pin for 1 second. At this rate, if DNA is spotted in the minimum space possible of about 0.32mm, it can stick about 8,100 DNA spots on the well plate. Analyzing the procedure: Movement starts. Pin washes, dries, and smears DNA on the well plate. Spots DNA onto 12 chips takes 2 minutes and 50 seconds.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.7-13
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• 2002

When a USB digital camera is used for PC video-conference applications, motion picture data need to be transferred to the PC through the USB port. Due to the mismatch between the data rates of the USB and the motion picture, data compression should be performed before the transmission from the USB. While many motion picture compression algorithms require large intermediate memory space, the JPEG algorithm does not need to store an entire frame for the compression. Instead, a relatively small buffer is required at the input of the JPEG compression engine to resolve the inconsistency between the orders of the inputted data and the consumed data. Data reordering can be easily implemented using a double buffering scheme, which still requires a considerable size of memory. In this paper, a novel memory management scheme is proposed to avoid the double buffering. The proposed memory architecture requires a small amount of memory and a simple address generation scheme, resulting in overall cost reduction.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.4944-4949
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• 2012

The purpose of this paper is concerned with a development of air gun for use at work. A air gun is the tool to remove of cutting fluid and workpiece chip in industrial field used machine tool. And it generally is used to shoot a jet of compressed air. Worker must prepare respectively air gun for suction and shooting a jet of compressed air. Therefore we has developed new air gun. In this paper we research for design and analysis of it. The air gun is composed of body, pipe, opening and shutting unit, turning unit, air tube and elements for fabrication. The developed air gun is experimented to confirm the efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.