• The Transactions of the Korea Information Processing Society
• /
• v.4 no.6
• /
• pp.1565-1575
• /
• 1997

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.12C
• /
• pp.1276-1281
• /
• 2002

Bellare and Rivest proposed the translucent cryptography which was a kind of key recovery system. Translucent cryptography is a system in which the third party can recover encrypted message with the probability p(0$\leq$p$\leq$1). The key recovery agency doesn't need to store the user's private key in advance. The balance between key recovery agency and user can be controlled by the value of p. For example, if p is set to be 0.4 then the key recovery agency can recover 40 out of 100 encrypted messages. In this paper, we show that user can easily deceive the key recovery agency in the translucent cryptography. Then we propose the solution of this problem.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.430-432
• /
• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.2
• /
• pp.51-59
• /
• 2002

In this paper, we studied the voice cryptograph system designed by the SEED algorithm for the safe transmission and receipt on the voice communication. Voice band signal converts to digital signal by the CODEC and DSP that applied the improved SEED algorithm encrypt the digital signal. The CODEC convert Encryption signal into analog voice signal. This voice signal is transmitted safely because of encryption signal even if someone wiretap. Receiver can hear the source voice, because the encryption signal decrypted using the SEED algorithm. In this paper, We designed the 32 round key instead of 16 round key in the SEED algorithm so that we improve the truncated differential probability from $2^{-143.1}$ to $2^{-286.6}$. 

• Proceedings of the Korea Information Processing Society Conference
• /
• 2002.04b
• /
• pp.1349-1352
• /
• 2002

Handset 을 통한 m-Commerce 시장의 확장과 더불어 커머스를 기반으로 한 물류서비스, 무선 인트라넷, 모바일 증권거래 등에 PDA(Personal Digital Assistant)를 정보단말로 이용하는 서비스가 늘어나면서 PDA 무선 보안솔루션 개발에 관련된 관심이 잇따르고 있다. 특히 PDA 무선 보안솔루션은 무선 PKI를 비롯해 암호화 솔루션, 백신, 파이어월 등 다양한 분야에서 독특한 기술이 개발되고 있으며 보안분야의 새로운 시장을 형성할 것으로 기대된다. PDA 무선 보안 솔루션은 증권, 뱅킹 등에서 시도되어지고 있는 Application layer 에서 암호/복호화 하는 방식, 유선과 동일하게 브라우저/ 웹서버에서 제공하는 SSL 암호화 방식, SSL v3 및 TLS v1 과 호환되는 자체 암호화 모듈 방식등의 3 가지로 크게 나누어 볼 수 있다. 본 논문에서는 WinCE OS 의 iPaq PDA 에 SSL v3 및 TLS v1 과 호환되는 자체 암호화 모듈 방식의 시스템을 설계한다. PDA 와 서버 간의 인증, 메시지 기밀성 및 무결성을 충족시킬 수 있는 보안 서비스를 제공하고 유선과 동일한 수준의 보안 수준을 유지하면서도 지금까지 무선 암호인증의 문제점이었던 소용량 무선단말기의 한계를 극복하는 PDA 용 무선 보안 솔루션을 설계하는데 목적을 두고 있다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2012.04a
• /
• pp.699-701
• /
• 2012

USB flash drive와 같은 이동형 저장매체는 한 손에 쏙 들어오는 작은 크기와 가벼운 무게로 뛰어난 휴대성을 제공하고 있다. 많은 사용자들은 자신의 데이터를 저장하기 위해 고용량을 제공하는 이동형 저장매체에 관심을 보이고 있다. 하지만 이동형 저장매체는 휴대성으로 인한 도난 및 분실당할수 있다. 개인 정보가 유출되는 등의 많은 문제들이 발생하고 있다. 인터넷의 발달과 클라우드 컴퓨팅 붐을 통하여 이동형 저장매체의 문제점을 해결할 수 있는 클라우드 스토리지 서비스가 급증하고 있다. 하지만 이러한 클라우드 스토리지 서비스는 인터넷이 가지고 있는 취약성 및 서버와 서버의 관리자의 비신뢰성 등의 문제를 가지고 있으며, 이로 인한 몇몇 사고가 발생하였다. 이러한 문제를 해결하기 위해서 클라우드 스토리지 환경에서는 데이터를 암호화 저장하고 이를 복호화 과정 없이 검색할 수 있는 검색 가능한 암호 기술의 필요성이 대두되고 있다. 하지만 기존의 검색가능 암호 기술은 사용자가 저장하고자 하는 데이터를 직접 업로드하고, 해당 자료를 필요에 따라 공유 하고, 공유대상이 변화되는 클라우드 스토리지 환경에서 비효율성을 가지고 있어 실제 서비스에 적용하기 힘든 단점을 가지고 있다. 따라서 본 논문에서는 클라우드 컴퓨팅 환경을 고려하여 검색가능한 암호화 색인 생성 및 이를 재암호화를 통해 다른 사용자와 안전하게 공유할 수 있는 검색가능한 재 암호화 시스템을 제안한다.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.31 no.6
• /
• pp.1237-1246
• /
• 2021

This paper is about Asynchronous Transfer Mode (ATM) cell security in which an Output Feedback (OFB) mode is applied to an AES block ciphers. ATM cells are divided into user data cells and maintenance cells, and each cell is 53 octets in size and consists of a header of 5 octets and a payload of 48 octets. In order to encrypt/decrypt ATM cells, the boundaries of cells must be detected, which is possible using the Header Error Control (HEC) field in the header. After detecting the boundary of the cell, the type of payload is detected using a payload type (PT) code to encrypt only the user cell. In this paper, a security method for ATM cells that satisfies the requirements of ISO 9160 is presented.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.10
• /
• pp.1125-1130
• /
• 2014

The quantity and quality of contents containing information are sharply increasing with the rising network speed. In line with this rapid growth of information volume, a new communication protocol using the chaotic signal that can protect contents in communication is proposed as follows. The chaos system has the characteristic of unpredictability due to the sensitive initial values and the similarity of the signals with noise. We configured two chaos systems $F(X_n,Y_n)$ and $G(A_n,B_n)$ that have such characteristics and designed a data communication method using as encryption channel the same chaos signals generated by synchronizing the chaos system G with the F signals. The proposed method was verified with the encryption and decryption of images. The proposed method is different from the existing encrypted communication methods and is expected to lay the foundation for future studies in related areas.is an example of ABSTRACT format.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.1
• /
• pp.315-318
• /
• 2005

Recently, the advent of wireless communication and other handhold devices like Personal Digital Assistants and smart cards have made in implementation of cryptosystems a major issue. One important aspect of modern day ciphers is the scope for hardware sharing between the encryption and decryption algorithm. The cellular Automata which have been proposed as an alternative to linear feedback shift registers(LFSRs) can be programmed to perform the operations without using any dedicated hardware. But to generalize and analyze CA is not easy. In this paper, we characterizes uniform/hybird complemented group CA with rules 195/153/51 that divide the entire state space into smaller spaces of maximal equal lengths. This properties can be useful in constructing key agreement algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.795-803
• /
• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.