• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.61-66
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• 2013

In this paper, temperature dependence of matching characteristics of $Si_3N_4$ MIM capacitor was analyzed in depth. The matching characteristics becomes worse as the temperature increases. That is, the matching coefficient of $Si_3N_4$ MIM capacitor at $25^{\circ}C$, $75^{\circ}C$, and $125^{\circ}C$ was 0.5870, 0.6151, and $0.7861%{\mu}m$, respectively. This phenomena is believed to be due to the reduction of the carrier mobility and the increase of the charge concentration of the inner capacitor at greater temperature. Therefore, the analysis of the matching characteristics of $Si_3N_4$ MIM capacitors at high temperatures is essential for application to analog and SoC (System on Chip) circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.23-30
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• 2000

To compensate the nonlinearity of electroabsorption modulator(EAM) resulting from its near exponential transfer function, a semiconductor optical amplifier(SOA) that has a log transfer function is used. Since the transfer function of SOA is inverse to that of EAM, the intermodulation distortion(IMD) of EAM can be reduced by cascading SOA to EAM. Also, the RF gain can be increased by the optical gain of SOA. For these reasons, spurious free dynamic range(SFDR) of EAM is enhanced by connecting SOA to EAM in series and operating in gain salutation region. To improve the nonlinearity compensation of EAM, the increased gain of SOA is required and the slope of gain saturation, the ratio of gain to input SOA power, needs to be steep. However, signal spontaneous beat noise that is the dominant system noise increases in proportion to the gain such that the SFDR of EAM is reduced. The higher the gain of SOA is, the more ASE is increased. Thus the noise level of system is increased and the following SFDR of EAM is decreased. The slope of gain saturation region and ASE of have trade-off relation and the optimization is achieved at 8㏈ optical gain. 9㏈ enhancement of SFDR of EAM is obtained. This scheme is easy to embody the linear EAM and the integration with three components (DFB-LD, EAM and SOA) offers many merits, such as low insertion loss, low chirping and low polarization sensitivity.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.422-435
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• 2005

Compared with analog broadcasting, digital broadcasting supports technical background to provide personalize the TV watching environment by offering broadcasting services that can adapt to viewers' preferences. However, current digital broadcasting shows limited services such as reservation recording, simple program guiding with an electronic program guide (EPG) on a personal video recorder system, and primitive data broadcasting by broadcasters. Therefore, the purpose of this paper is to suggest a new broadcasting environment which gives a person facility and a difference fur watching TV by serving enhanced personalized services. For that reason, we propose an intelligent broadcasting system which can minimize viewer's actions, and enhanced broadcasting services which are based on understanding of the semantics of broadcasting contents. To implement the system, agent technology as well as the MPEG-7 and TV-Anytime Forum (TVAF) are employed. For content-level services, real-time content filtering and personalized video skimming are designed and implemented. To verify the usefulness of the proposed system, we demonstrate it with a test-bed on which content-level personalized services are implemented.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.2
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• pp.57-64
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• 2015

At the case of peak threshold algorithm, 3-axes data should sample step data over 20 Hz to get sufficient accuracy. But most of the digital sensors like 3-axes accelerometer have very low sampling rate caused by low data communication speed on limited SPI or $I^2C$ bandwidth of the low-cost MPU for ubiquitous devices. If the data transfer rate of the 3-axes accelerometer is getting slow, the sampling rate also slows down and it finally degrades the data accuracy. In this study, we proved there is a distinct functional relation between the sampling rate and threshold on the peak threshold step detection algorithm under the 20Hz frequency, and made a threshold function through the experiments. As a result of experiments, when we apply threshold value from the threshold function instead of fixed threshold value, the step detection error rate can be lessen about 1.2% or under. Therefore, we can suggest a peak threshold based new step detection algorithm with threshold function and it can enhance the accuracy of step detection and step count. This algorithm not only can be applied on a digital step counter design, but also can be adopted any other low-cost ubiquitous sensor devices subjected on low sampling rate.

• The Journal of the Convergence on Culture Technology
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• v.9 no.6
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• pp.41-47
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• 2023

This study was conducted to determine the effect of an exercise program applied to prevent musculoskeletal changes that occur due to aging on pain, muscle strength, balance ability, and falling efficacy in elderly women. An exercise program including quadriceps setting exercise, bridge exercise, resistance band exercise, and foam roller exercise was applied to elderly women aged 65 years or older once a week for 8 weeks. A visual analog scale was used to evaluate pain, muscle strength was evaluated using a digital muscle strength meter, balance ability was measured using the Berg balance scale, and fear of falling was evaluated using the fall efficacy scale. As a result of the study, compared to before the experiment, pain in the lower back and knee area was significantly reduced, the strength of the quadriceps femoris and gluteus maximus was significantly increased, and balance ability and falling efficacy were significantly improved. In conclusion, application of a program that includes various exercise methods has a positive effect on the physical activity of elderly women by strengthening the musculoskeletal system. Additionally, in order to prevent physical changes due to aging, an exercise program that includes various exercise methods that can strengthen the musculoskeletal system should be applied.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.52-59
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• 2007

In this paper, we analyzed and measured implant isolation characteristics for a 1.25 Gbps monolithic integrated hi-directional (M-BiDi) optoelectronic system-on-a-chip, which is a key component to constitute gigabit passive optical networks (PONs) for a fiber-to-the-home (FTTH). Also, we derived an equivalent circuit of the implant structure under various DC bias conditions. The 1.25 Gbps M-BiDi transmit-receive SoC consists of a laser diode with a monitor photodiode as a transmitter and a digital photodiode as a digital data receiver on the same InP wafer According to IEEE 802.3ah and ITU-T G.983.3 standards, a receiver sensitivity of the digital receiver has to satisfy under -24 dBm @ BER=10-12. Therefore, the electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysed and measured results of the implant structure, the M-BiDi SoC with the implant area of 20 mm width and more than 200 mm distance between the laser diode and monitor photodiode, and between the monitor photodiode and digital photodiode, satisfies the electrical crosstalk level. These implant characteristics can be used for the design and fabrication of an optoelectronic SoC design, and expended to a mixed-mode SoC field.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.43-53
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• 2003

Unlike in analog display devices, the physical screen resolution in digital devices are fixed from the manufacturing. It is a weak point on digital devices. The screen resolution displayed in digital display devices is varied. Thus, interpolation or decimation of the resolution on the display is needed to make the input pixels equal to the screen resolution., This process is called image scaling. Many researches have been developed to reduce the hardware cost and distortion of the image of image scaling algorithm. In this paper, we proposed a Winscale algorithm. which modifies the scale up/down in continuous domain to the scale up/down in discrete domain. Thus, the algorithm is suitable to digital display devices. Hardware implementation of the image scaler is performed using Verilog XL and chip is fabricated in a 0.5${\mu}{\textrm}{m}$ Samsung SOG technology. The hardware costs as well as the scalabilities are compared with the conventional image scaling algorithms that are used in other software. This Winscale algorithm is proved more scalable than other image-scaling algorithm, which has similar H/W cost. This image-scaling algorithm can be used in various digital display devices that need image scaling process.