• Journal of the Korean Society for Precision Engineering
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• v.30 no.1
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• pp.128-133
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• 2013

Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.

• Journal of IKEEE
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• v.13 no.2
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• pp.126-131
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• 2009

To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.115-116
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• 2005

Si nanowires (NWs) were fabricated in vacuum furnace by using a Nd:YAG pulsed laser with the wavelength of 325 nm. Commercial p-type Si wafer is used for target, and any catalytic materials are not used. Scanning electron microscopy (SEM) images indicate that the diameters of Si NWs ranged from 10 to 150 nm. Si NWs have various size and shape with a substrate position inside a furnace, and their morphologic construction is reproducible. The formation mechanism of the NWs is discussed.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.1-6
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• 2006

We fabricated Si nano-wire MOSFET by using the conventional photolithography with a $1.5{\mu}m$ resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.48-48
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• 2018

습도는 대기중에 분포되어있는 물 분자의 양으로 사람이 살아가는데 있어 막대한 영향을 주는 환경적 요소중 하나이다. 산업적 가스의 순도에 막대한 영향을 끼치기도 하고, 반도체 산업에서 불량률과도 밀접한 관련이 있다. 또한, 식품학이나 기상학, 농사와도 밀접한 관련이 있어서 습도를 측정하는 것은 중요시 되고 있다. 이를 위해서 많은 물질들이 사용되고, 연구되었다. 산화 구리, 산화 아연, 산화 납 등의 산화금속 물질들이나 전도성 고분자, 실리콘 기반의 물질들이 주로 사용되고 있는데, 그 중 산화 금속이 쉬운 합성 방법과 낮은 단가, 명확한 작동 원리로 인해 널리 사용되고 있다. 산화 아연의 경우 넓은 direct band gap energy와 우수한 내화학성으로 인해 주로 사용되는데 그 중 1차원 물질인 nanowire의 경우 비등성 구조와 높은 비표면적을 갖는 특성으로 인해 산화 아연의 nanowire 구조가 많이 사용된다. 본 연구에서는 열처리 공정을 이용하여 산화아연의 nanowire 구조를 합성하였고, 합성된 nanowire는 양쪽의 미세전극을 직접적으로 연결하여 간편한 방식으로 소형 소자를 만들 수 있다는 장점이 있다. 열처리 공정 이전에 전기도금 방식을 이용하여 아연층을 증착 하였다. 전기도금 조건은 0.1 M의 염화 아연과 1 M의 염화 칼륨으로 구성된 용액에 -1.1 V를 인가하였다. 합성된 아연층은 열처리 공정에 의해 산화아연의 nanowire 구조체로 변환되고, SEM (scanning electron microscope)를 통해 표면 형상을 관찰 하였고, XRD (X-ray diffraction)을 통해 미세구조를 확인하였다. -1 V부터 1 V 범위의 전압을 흘려주어 형성된 소자의 전기적 특성을 확인하였고, 1 V를 인가하였을 때, 습도 변화에 따른 센서 소자의 저항변화를 통해 습도 센서로서의 특성을 확인 하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.2
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• pp.101-105
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• 2007

We have synthesized silicon nanowires by using RFCVD(Radio Frequency Chemical Vapor Deposition) system on Au deposited p-type Si(100) wafers, and investigated their physical and electrical properties. The silicon nanowires had been grown in the atmospheres of $H_{2},\;N_{2}\;and\;SiH_{4}$ at 10 Torr at the substrate temperatures of $700{\pm}5^{\circ}C\;and\;810{\pm}5^{\circ}C$ respectively. FE-SEM analysis revealed that diameters of the silicon nanowires are $50{\sim}60nm$ with the length of several ${\mu}m$. XRD analysis showed that the growth direction of the nanowires is Si[111]. Field emission characteristics showed that the turn-of voltages at the current of $0.01\;mA/cm^{2}$ are $10\;V/{\mu}m\;and\;8.5\;V/{\mu}m$ for the wires grown at $700{\pm}5^{\circ}C\;and\;810{\pm}5^{\circ}C$, respectively.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.26 no.6
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• pp.409-413
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• 2013

In this paper, we device stress-diffusion full coupling multiscale analysis method for battery electrode simulation. In proposed method, the diffusive and mechanical properties of electrode material depend on Li concentration are estimated using density function theory(DFT) simulation. Then, stress-diffusion full coupling continuum formulation based on finite element method(FEM) is constructed with the diffusive and mechanical properties calculated from DFT simulation. Finally, silicon nanowire anode charge and discharge simulations are performed using the proposed method. Through numerical examples, the stress-diffusion full coupling method shows more resonable results than previous one way continuum analysis.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.183.2-183.2
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• 2013

저항이 낮고 투과도가 일정한 투명전도막(TCF)의 내구성을 향상 및 유지 시키는 연구는 상업화에 가장 필요한 연구 분야이다. 그 중 탄소나노튜브(CNT)와 실버나노와이어(AgNW)를 섞어 만든 CNT-AgNW는 우수한 광투과성과 내화학성 및 균일한 전기 전도성을 갖고 있고 그 기반의 투명전도막은 기존의 ITO 및 CNT 박막보다 우수한 유연성을 갖기 때문에 차세대 플렉시블 디스플레이 소재로서 많은 관심을 모으고 있다. 본 연구는 PET를 이용한 CNT-AgNW로 제작된 투명전도막 위에 물성 및 두께 따른 하드오버 코팅을 통한 내구성 개선 및 유지를 연구하였다. 하드오버 코팅 물질로는 실로콘계 하이브리드 투명 하드코팅 소재를 기본으로 하고 용매 및 용질의 합성 온도를 제어하고 코팅막의 두께(Thin, Thick)를 조절을 통해 내구성 개선을 증진시키려 하였다. 연구결과 물성 향상에 가장 많은 영향을 끼치는 것은 CNT-AgNW 코팅층과 하드오버 코팅층과의 젖음성으로, 그 젖음성이 증가할수록 투과도 및 전기전도도가 향상되는 것을 관찰하였다. 분석 결과, 용매의 비점 및 비중, 용질의 합성 온도가 하드오버코팅 젖음성에 가장 많은 영향을 주는 것을 확인하였다. 또한 항온 항습($85^{\circ}C/85%$) 환경에서 240시간 이상 내구성 테스트 결과 하드오버코팅 물질 중 고온합성 및 고비점 용매를 이용하고 thick 조건이 Thin조건보다 투명전도성 평가 지수(${\sigma}DC/{\sigma}OP$)가 향상 되었다. 또한 Thin에서 면저항(${\Omega}/{\square}$) 변화율이 10% 이상을 보인 반면, Thick에서는 10% 이내의 변화율 유지를 확인하였다.

• Journal of Adhesion and Interface
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• v.25 no.2
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• pp.63-68
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• 2024

In this study, the contamination of gold(Au) wire according to the types of rinse applied for surface treatment in the wire bonding process is investigated and confirmed. For the surface treatment, rinses containing silicon(Si) or those based on organic materials are mainly employed. To identify their effects, surface treatment is conducted on Au wire using two types of rinse at a 1.0 wt% concentration, referred to as Si-including and Oil-based rinse-coated Au wire. Subsequently, a simulation experiment is performed to verify the reactivity of dust containing Si components that could occur in the semiconductor process. Through optical microscopy (OM) and scanning electron microscopy(SEM) analysis, it is observed that a larger amount of dust is adsorbed on the surface of Si-including rinse-coated Au wire compared with the Oil-based rinse-coated Au wire. This is attributed that the rinse containing Si components is relatively polar, causing polar interactions with dust, which also has polarity. Therefore, it is expected that using a rinse without Si components can reduce contamination caused by dust, thereby decreasing the defect rate in the practical wire bonding process.

• Journal of the Korean institute of surface engineering
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• v.49 no.3
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• pp.301-306
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• 2016

The effects of nanotexturing and post-etching on the reflection and quantum efficiency properties of diamond wire sawn (DWS) multicrystalline silicon (mc-Si) solar cell have been investigated. The chemical solutions, which are acidic etching solution (HF-$HNO_3$), metal assisted chemical etching (MAC etch) solutions ($AgNO_3$-HF-DI, HF-$H_2O_2$-DI) and post-etching solution (diluted KOH at $80^{\circ}C$), were used for micro- and nano-texturing at the surface of diamond wire sawn (DWS) mc-Si wafer. Experiments were performed with various post-etching time conditions in order to determine the optimized etching condition for solar cell. The reflectance of mc-Si wafer texturing with acidic etching solution showed a very high reflectance value of about 30% (w/o anti-reflection coating), which indicates the insufficient light absorption for solar cell. The formation of nano-texture on the surface of mc-Si contributed to the enhancement of light absorption. Also, post-etching time condition of 240 s was found adequate to the nano-texturing of mc-Si due to its high external quantum efficiency of about 30% at short wavelengths and high short circuit current density ($J_{sc}$) of $35.4mA/cm^2$.