• Title/Summary/Keyword: 신호 최적화

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The Development of Traffic Queue Length Estimation Algorithm Using the Occupancy Rates (점유율을 이용한 대기행렬길이 추정 알고리즘 개발)

  • Kang Jihoon;Oh Young-Tae;Kang Jeung-Sik
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.4 no.2 s.7
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    • pp.13-22
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    • 2005
  • The purpose of this research is how to estimate the traffic queue length in the signal intersection accurately. The current traffic queue length algorithm in COSMOS has been using the congestion diagram which comes from the speed of an average separated vehicle - using average vehicle length and the occupancy time from loop detectors. So some errors were occurred by the speed estimation method using average vehicle lengths. And Operators had been difficult to optimize some variables for measuring the traffic queue length estimation algorithm in COSMOS. Therefore the traffic queue length estimation algorithm on the basis of the relation between distances and occupancy rates from loop detectors was developed in this thesis. This thesis had the advantage of using occupancy rates which came out from loop detectors easily and no need to optimize some variables for the established algorithm in COSMOS. And the results of testing this algorithm in some sites which had installed COSMOS system showed better results than COSMOS system's results. But it was noted that further studies which carry it out in various sites and under various cases are necessary for applying to actual intersections.

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Optimization and Performance Analysis of Partial Multiplexing (부분 다중화의 성능 분석 및 최적화)

  • Kim, Seong Hwan;Ban, Tae Won;Jung, Bang Chul
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.7
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    • pp.1589-1596
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    • 2013
  • Recently, spectral efficiency or reliability is required to be improved in the scenario of multiple access. In this paper, we consider a scenario where two source nodes access one destination node. Different with conventional multiple access studies, in our research, a part of the allocated resource is shared by two source nodes and this scheme is called partial multiplexing. Let $R_s$ denote the ratio of the amount of the shared resource to that of the resource allocated to each user. We analyze and optimize the performance of the partial multiplexing in term of $R_s$. We show that the optimal $R_s$ to maximize the throughput is 1 or 0 based on approximated bit error rate (BER). In addition, if we set a constraint on frame error rate (FER), $R_s$ can have a value between 0 and 1. We also find the approximated $R_s$ to meet the constraint as a closed form. Partial multiplexing can be a novel multiple access scheme.

Run-time Memory Optimization Algorithm for the DDMB Architecture (DDMB 구조에서의 런타임 메모리 최적화 알고리즘)

  • Cho, Jeong-Hun;Paek, Yun-Heung;Kwon, Soo-Hyun
    • The KIPS Transactions:PartA
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    • v.13A no.5 s.102
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    • pp.413-420
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    • 2006
  • Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit (클록 보정회로를 가진 1V 1.6-GS/s 6-bit Flash ADC)

  • Kim, Sang-Hun;Hong, Sang-Geun;Lee, Han-Yeol;Park, Won-Ki;Lee, Wang-Yong;Lee, Sung-Chul;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.9
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    • pp.1847-1855
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    • 2012
  • A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

Using a H/W ADL-based Compiler for Fixed-point Audio Codec Optimization thru Application Specific Instructions (응용프로그램에 특화된 명령어를 통한 고정 소수점 오디오 코덱 최적화를 위한 ADL 기반 컴파일러 사용)

  • Ahn Min-Wook;Paek Yun-Heung;Cho Jeong-Hun
    • The KIPS Transactions:PartA
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    • v.13A no.4 s.101
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    • pp.275-288
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    • 2006
  • Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

Role of FAK Phosphorylation in Cobalt Chloride-Induced Epithelial-to-Mesenchymal-Like Transition (Cobalt chloride에 의해 유도되는 상피-중간엽 이행에서의 국소부착 단백질의 인산화의 역할 규명)

  • Nam, Ju-Ock
    • Journal of Life Science
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    • v.21 no.2
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    • pp.286-291
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    • 2011
  • Hypoxia is a common condition found in a wide range of solid tumors and is often associated with metastasis and poor clinical outcomes. In the present study, we found that HIF-$1{\alpha}$ was induced by cobalt chloride (500 ${\mu}M$) treatment on human lung cancer cells, A549 and H460, for 24 hr. However, cobalt chloride (500 ${\mu}M$) did not affect cell proliferation of A549 and H460 in 48 hr. Cobalt chloride (500 ${\mu}M$) additionally induced epithelial-to-mesenchymal-like transition (EMT) such as reduced E-cadherin expression and increased ${\alpha}$-SMA expression. These results were confirmed by immunofluorecence experiment in H460 cells. E-cadherin was localized on the outer cell membrane. However, when the cells were treated with 500 ${\mu}M$ cobalt chloride for 24 hr, diffuse E-cadherin staining was observed, characteristic of a migratory mesenchymal phenotype. We also found that cobalt chloride induced integrin ${\beta}3$ expression and FAK phosphorylation in human lung cancer cells using western blotting and FACS anlaysis. Our data suggest that integrin ${\beta}3$-induced FAK phosphorylation may be developed into target molecules for blocking tumor metastasis.

DNN-Based Dynamic Cell Selection and Transmit Power Allocation Scheme for Energy Efficiency Heterogeneous Mobile Communication Networks (이기종 이동통신 네트워크에서 에너지 효율화를 위한 DNN 기반 동적 셀 선택과 송신 전력 할당 기법)

  • Kim, Donghyeon;Lee, In-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.10
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    • pp.1517-1524
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    • 2022
  • In this paper, we consider a heterogeneous network (HetNet) consisting of one macro base station and multiple small base stations, and assume the coordinated multi-point transmission between the base stations. In addition, we assume that the channel between the base station and the user consists of path loss and Rayleigh fading. Under these assumptions, we present the energy efficiency (EE) achievable by the user for a given base station and we formulate an optimization problem of dynamic cell selection and transmit power allocation to maximize the total EE of the HetNet. In this paper, we propose an unsupervised deep learning method to solve the optimization problem. The proposed deep learning-based scheme can provide high EE while having low complexity compared to the conventional iterative convergence methods. Through the simulation, we show that the proposed dynamic cell selection scheme provides higher EE performance than the maximum signal-to-interference-plus-noise ratio scheme and the Lagrangian dual decomposition scheme, and the proposed transmit power allocation scheme provides the similar performance to the trust region interior point method which can achieve the maximum EE.

An 8b 240 MS/s 1.36 ㎟ 104 mW 0.18 um CMOS ADC for High-Performance Display Applications (고성능 디스플레이 응용을 위한 8b 240 MS/s 1.36 ㎟ 104 mW 0.18 um CMOS ADC)

  • In Kyung-Hoon;Kim Se-Won;Cho Young-Jae;Moon Kyoung-Jun;Jee Yong;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.1
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    • pp.47-55
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    • 2005
  • This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems (초광대역 통신시스템 응용을 위한 이중채널 6b 1GS/s 0.18um CMOS ADC)

  • Cho, Young-Jae;Yoo, Si-Wook;Kim, Young-Lok;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.47-54
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    • 2006
  • This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

An Incident-Responsive Dynamic Control Model for Urban Freeway Corridor (도시고속도로축의 유고감응 동적제어모형의 구축)

  • 유병석;박창호;전경수;김동선
    • Journal of Korean Society of Transportation
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    • v.17 no.4
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    • pp.59-69
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    • 1999
  • A Freeway corridor is a network consisting of a few Primary longitudinal roadways (freeway or major arterial) carrying a major traffic movement with interconnecting roads which offer the motorist alternative paths to his/her destination. Control measures introduced to ameliorate traffic performance in freeway corridors typically include ramp metering at the freeway entrances, and signal control at each intersections. During a severe freeway incident, on-ramp metering usually is not adequate to relieve congestion effectively. Diverting some traffic to the Parallel surface street to make full use of available corridor capacity will be necessary. This is the purpose of the traffic management system. So, an integrated traffic control scheme should include three elements. (a)on-ramp metering, (b)off-ramp diversion and (c)signal timing at surface street intersections. The purpose of this study is to develop an integrated optimal control model in a freeway corridor. By approximating the flow-density relation with a two-segment linear function. the nonlinear optimal control problem can be simplified into a set of Piecewise linear programming models. The formulated optimal-control Problem can be solved in real time using common linear program. In this study, program MPL(ver 4.0) is used to solve the formulated optimal-control problem. Simulation results with TSIS(ver 4.01) for a sample network have demonstrated the merits of the Proposed model and a1gorithm.

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