• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.735-742
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• 2006

In this paper, we explain the operation scheme and fixed-point design method of DFE (Digital Front End), which performs DC offset compensation, automatic frequency control, and automatic gain control over the input signal to the UE (User Equipment) receiver of IEEE 802.16e OFDMA-TDD system. Then, we analyze the performance of DFE under ITU-R M. 1225 Veh-A 60km/h channel environment. To optimize the fixed-point design of DFE, we reduce the number of bit resulted from calculation without performance degradation, leading to the decreased complexity of the operation in H/W, and design the Loop filter with considering trade-off between the Acquisition time and the Stability.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.145-150
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• 2016

The capability of accurate positioning and tracking is necessary to implement an unmanned autonomous driving system. The moving-baseline GPS Technique is a promising candidate to mitigate positioning errors of conventional GPS system. It provides accurate positioning data based on the phase difference between received signals from multiple GPS antennas mounted on the same platform. In this paper, we propose a dual-band dual-circularly-polarized antenna suitable for the moving-baseline GPS. The proposed antenna operates at GPS L1 and L2 bands, and fed by the side of the antenna instead of the bottom. The antenna is firstly designed by calculating theoretical values of key parameters, and then optimized by means of 3D full-wave simulation software. Simulation and measurement results show that the optimized antenna offers 6.1% and 3.7% bandwidth at L1 and L2, respectively, with axial ratio bandwidth of more than 1%. The size of the antenna is $73mm{\times}73mm{\times}6.4mm$, which is small and low-profile.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.570-575
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• 2004

In the underwater acoustic systems. we can receive signals and retrieve information about a target by using a beamforming method. The most important thing in the beamforming is finding the way to optimize the mainlobe beamwidth and the sidelobe level to the desired value. One of the prominent results of beamforming method. which has been studied. is Philip's weighting function method(1) . Philip's method adaptively adjusts its weights of array to meet the desired mainlobe beamwidth and sidelobe level. It is very similar to the design method in adaptive filter. However. this method cannot easily bring us to the desired sidelobe level due to complementary relation between mainlobe beamwidth and sidelobe level. In this paper, we propose a new algorithm using partial constrained adaptation. This method makes us circumvent the above problem and meet the specification of design easily. The proposed algorithm presents a Pattern synthesis that designer can easily control the mainlobe beamwidth and the sidelobe level to the desired value while calculation time to converge is decreasing.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.4
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• pp.87-94
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• 2013

This study estimated the changes in delays and speeds of vehicles in exclusive bus lane and road when the High Occupancy Vehicles(HOV) use the median bus lane. Synchro simulation tool was used to optimize the traffic signal time on the network and VISSIM was applied to simulate various scenarios. Here, drivers behavior parameters in VISSIM was optimized using Simultaneous Perturbation Stochastic Approximation(SPSA) algorithm in order to represent real traffic condition. Based on the simulation results, the delay in Doan daero was decreased when the volume of HOV in current condition runs on the median bus lane, whereas delay in Doan dongro was increased in all scenarios. The changes in bus speed was not sharply decreased for both study sites, even though the number of HOV increased to 10%. Thus, it could be allowed that the HOV use the median bus lane in Doan dongro and Doan daero. Future research tasks include studying about changes in delay when the HOV use the curb bus lane.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.56-66
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• 1998

This paper investigates a neuro-controller combined in parallel with a conventional linear controller of PID type in order to control nonminimum phase systems more efficiently. The objective is to minimize overall position errors as well as to maintain small undershooting. A costfunction is proposed with two conflict objectives. The neuro-controller is trained off-line with evolutionary programming(EP) in such a way that it becomes optimal by minimizing the given cost function through global evaluation based on desired control performance during the whole training time interval. However, it is not easy to find an optimal solution which satisfies individual objective simultaneously. With the concept of Pareto optimality and EP, we train the proposed controller more effectively and obtain a valuable set of optimal solutions. Simulation results show the efficacy of the proposed controller in a viewpoint of improvement of performance of a step response like fast settling time and small undershoot or overshoot compared with that of a conventional linear controller.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.1
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• pp.329-332
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• 2012

LEDs are using widely in a field of illumination, LCD LED backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. To achieve high performance LEDs, one needs to enhance output power, reduce operation voltage, and improve device reliability. In this paper, we have proposed that the optimum design and specialized process could improve the performance of LED chip. It was showed an output power of 7cd and input supplied voltage of 3.2V by the insertion technique of current blocking layer. In this paper, GaN-based LED chip which is built on the sapphire epi-wafer by selective MOCVD were designed and developed. After that, their performances were measured. It showed the output power of 7cd more than conventional GaN-based chip. It will be used the lighting source of a medical equipment and LCD LED TV with GaN-based LED chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3A
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• pp.217-224
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• 2010

In this paper, we propose a hard handover algorithm for a base station's self-optimization, one of the automatic operational technologies for the 3GPP LTE systems. The proposed algorithm simultaneously considers a mixed target sell selection method for optimal selection and a multiple parameter based active hysteresis method with the received signal strength from adjacent cells and the cell load information of the candidate target cells from information exchanges between eNBs through X2 interface. The active hysteresis method chooses optimal handover hysteresis value considering the costs of the various environmental parameters effect to handover performance. The algorithm works on the optimal target cell and the hysteresis value selections for a base station's automatic operational optimization of the LTE system with the gathered informaton effects to the handover performance. The simulation results show distinguished handover performances in terms of the most important performance indexes of handover, handover failure rate and load balancing.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.448-448
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• 2012

최근에 pH 감지막의 감지감도특성을 평가하기 위해 electrolyte insulator semiconductor (EIS) 구조가 유용하게 이용되고 있다. EIS는 간단한 구조와 pH 용액에 빠른 응답속도, 낮은 단가 및 집적이 용이하다는 장점이 있다. EIS 구조에서 화학적 용액에 대한 감지감도 평가 중 가장 중요하게 작용하는 부분이 감지막이다. 이 감지막은 감지 대상 물질과 물리적으로 직접 접촉되는 부분으로서 일반적으로 기계적/화학적 강도가 우수한 실리콘 산화막($SiO_2$)이 많이 사용되어져 왔다. 최근에는 기존의 $SiO_2$ 보다 성능이 향상된 감지막을 개발하기 위하여 $Al_2O_3$, $HfO_2$, $ZrO_2$, 그리고 $Ta_2O_5$와 같은 고유전 상수(high-k)를 가지는 물질들을 EIS 센서의 감지막으로 이용하는 연구가 활발하게 진행되고 있다. High-k 물질 중 $Al_2O_3$는 산성에서 알칼리성 영역까지의 넓은 화학안정성을 가지며 화학용액에 대해 내구성이 우수한 특성을 가진다. $HfO_2$은 내식성이 뛰어나며 출력특성이 높은 장점을 가진 물질이다. 본 실험에서는 특성이 다른 두 물질을 EIS의 감지막으로 각각 사용하여 두께에 따른 의존성을 평가하였다. 제작한 EIS 구조의 pH 센서를 바이오 센서에 적용하였을 때 신호대 잡음비(SNR: signal to noise)가 여전히 취약하다는 문제점이 있었다. 이런 문제점을 보완하기 위하여 감지막의 물리적 두께는 점점 얇아지게 되었고 그 결과 높은 출력 특성을 얻게 되었지만, 감지막이 얇아짐에 따라서 화학 용액 중의 이온 침투로 인한 감지막 자체의 손상 또한 심각한 문제로 대두되었다. 이로 인해 최적화 된 감지막의 두께를 얻을 필요가 있다. 결론적으로 $Al_2O_3$, $HfO_2$ 두 감지막 모두 두께가 23 nm일 때 가장 우수한 특성을 보였으며, $Al_2O_3$를 감지막으로 사용하였을 경우 화학적 용액에 대해 내구성이 뛰어났고, $HfO_2$을 사용하였을 때에는 화학적 용액에 대한 안정성 보다는 pH 용액변화에 따른 향상된 감지감도특성을 보였다.