• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.98-105
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• 2007

In this paper, we propose a timing detector using suboptimal maximum likelihood method. The proposed method has an simple reference signal generator. Additionally, timing detector's gain of the proposed method is the same to Early-Late gate and ML method. We reveal that tracking range of time tracker is narrow because of using data-decision, that is, tracking range is ${\pm}0.06ns$ for the 4-order Gaussian monocycle with 0.7ns pulse width. Therefore we can find that searcher must have very accurate acquisition procedure. When estimating a performance of time tracker, we consider a jitter in transmitter and receiver's pulse generation process as well as background noise. By using computer simulation, we propose mean/variance of timing detector and tracking process. Also we consider a mobility in tracking process, i.e., timing error modeled ramp function. In order to propose a performance of time tracker, we consider only one correlation demodulator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.6
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• pp.487-497
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• 2019

It is very difficult to detect ballistic missiles because of small cross-sections of the radar and the high maneuverability of the missiles. In addition, it is very difficult to recognize and intercept warheads because of the existence of debris and decoy with similar motion parameters in each flight phase. Therefore, feature vectors based on the maneuver, the micro-motion according to flight phase are needed, and the two types of features must be fused for the efficient recognition of ballistic warhead regardless of the flight phase. In this paper, we introduce feature vectors appropriate for each flight phase and an effective method to fuse them at the feature vector-level and classifier-level. According to the classification simulations using the radar signals predicted by the CAD models, the closer the warhead was to the final destination, the more improved was the classification performance. This was achieved by the classifier-level fusion, regardless of the flight phase in a noisy environment.

• The Journal of the Acoustical Society of Korea
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• v.38 no.4
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• pp.371-377
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• 2019

In this paper, we present the sea trial results of long distance underwater acoustic communication in the East Sea, October 2018. One transmitter and sixteen vertical array receivers were used to collect underwater acoustic communication signals, and the maximum distance between the transmitter and the receiver was 90 km. Information was transmitted by BFSK (Binary Frequency Shift Keying) and BCSK (Binary Chirp Shift Keying) method, which are typical digital frequency modulation techniques. Experimental results show that there is no error in all cases at the transmission distance of 60 km, and BFSK and BCSK have average uncoded bit error rate of 0.0197 and 0.0007 respectively without channel coding at 90 km transmission distance.

• The Journal of the Acoustical Society of Korea
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• v.26 no.8
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• pp.415-425
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• 2007

This paper proposes a method of underwater source localization using the wideband interference patterns matching. By matching two interference patterns in the spectrogram, it is estimated a ratio of the range from source to sensor5, and then this ratio is applied to the Apollonius circle. The Apollonius circle is defined as the locus of all points whose distances from two fixed points are in a constant value so that it is possible to represent the locus of potential source location. The Apollonius circle alone, however still keeps the ambiguity against the correct source location. Therefore another equation is necessary to estimate the unique locus of the source location. By estimating time differences of signal arrivals between source and sensors, the hyperbola equation is used to get the cross point of the two equations, where the point being assumed to be the source position. Simulations are performed to get performances of the proposed algorithm. Also, comparisons with real sea experiment data are made to prove applicability of the algorithm in real environment. The results show that the proposed algorithm successfully estimates the source position within an error bound of 10%.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.6
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• pp.401-410
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• 2020

In this study, a real-time Tactical UAS position compensation system based on image information developed to compensate for the weakness of location navigation information during GPS signal interference and jamming / spoofing attack is described. The Tactical UAS (KUS-FT) is capable of automatic flight by switching the mode from GPS/INS integrated navigation to DR/AHRS when GPS signal is lost. However, in the case of location navigation, errors accumulate over time due to dead reckoning (DR) using airspeed and azimuth which causes problems such as UAS positioning and data link antenna tracking. To minimize the accumulation of position error, based on the target data of specific region through image sensor, we developed a system that calculates the position using the UAS attitude, EO/IR (Electric Optic/Infra-Red) azimuth and elevation and numerical map data and corrects the calculated position in real-time. In addition, function and performance of the image information based real-time UAS position compensation system has been verified by ground test using GPS simulator and flight test in DR mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.26-34
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• 1999

According to increase of nonlinear power electronics equipment, active power filters have been researched and developed for many years to compensate harmonic disturbances and reactive power. However the commercial of active power filter is being proceeded slowly, because the cost of active power filter compared to the passive filter for harmonic and reactive power compensation is expensive. Especially, the use of DSP (Digital Signal Processing) chip, which is frequently used to control 3-phase active power filter, is a factor of increasing the cost of active power filters. On the other hand, the use of only analog controller makes the controller's circuits much more complicate and depreciates the flexibilities of controller. In this paper, a controller with low cost for 5[kVA] 3-phase active power filter system is designed. To reduce the expense of active filter system, the presented controller is composed of digital control part using Intel 80C196KC $\mu$P and analog control part using hysteresis controller for current control. Characteristic analysis of designed controller for active filter system is performed by computer simulation and compensating characteristics of the designed controller are verified by experiment.tegy can apply to the vector control, leading to better output torque capability in the ac motor drive system. This strategy is that in the overmodulation range, the d-axis output current is given a priority to regulate the flux well, instead the q-axis output curent is sacrificed. Therefore, the vector control even in the overmodulation PWM operation can be achieved well. For this purpose, the d-axis output voltage of a current controller to control the flux is conserved. the q-axis output voltage to control the torque is controlled to place the reference voltage vector on the hexagon boundary in case of the overmodulation. The validity of the proposed overall scheme is confirmed by simulation and experiments for a 22[kW] induction motor drive system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.174-179
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• 2013

This paper presents a capacitor loaded tunable bandpass chip filter using multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The SOI-CMOS switched capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5GHz. The proposed on-chip filter is implemented in 0.18-${\mu}m$ SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only $4mm{\times}2mm$ (i.e., $0.177{\lambda}g{\times}0.088{\lambda}g$), where ${\lambda}g$ denotes the guided wave length of the $50{\Omega}$ microstrip line at center frequency. The measured insertion loss (S21)is about 5.1dB and 6.9dB at 5.4GHz and 4.5GHz, respectively. The designed filter shows out-of-band rejection greater than 20dB at 500MHz offset from center frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.1028-1036
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• 2008

In the OFDM system, IQ imbalance problem happens at the RF front-end of transceiver, which degrades the BER(bit error rate) performance because it affects the constellation in the received signal. Also, phase noise is generated in the local oscillator of transceivers and it destroys the orthogonality between the subcarriers. Conventional PNS algorithm is effective for phase noise suppression, but it is not useful anymore when there are jointly IQ(In-phase and Quadrature) imbalance and phase noise. Therefore, in this paper, we analyze the effect of IQ imbalance and phase noise generated in the down-conversion of the receiver. Then, we estimate and compensate the IQ imbalance and phase noise at the same time. Compared with the conventional method that IQ imbalance after IFFT is estimated and compensated in front of FFT via the feedback, this proposed method extracts and compensates effect of IQ imbalance after FFT stage. In case IQ imbalance and phase noise exist at the same time, we can decrease complexity because it is needless to use elimination of IQ imbalance in time domain and training sequences and preambles. Also, this method shows that it reduces the ICI and CPE component using adaptive forgetting factor of MMSE after FFT.