• The Journal of the Korea Contents Association
• /
• v.16 no.3
• /
• pp.91-101
• /
• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.2
• /
• pp.333-340
• /
• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.3
• /
• pp.23-31
• /
• 2010

The increasing demands on low-power, and low-complexity video encoder have been motivating extensive research activities on distributed video coding (DVC) in which the encoder compresses frames without utilizing inter-frame statistical correlation. In DVC encoder, contrary to the conventional video encoder, an error control code compresses the video frames by representing the frames in the form of syndrome bits. In the meantime, the DVC decoder generates side information which is modeled as a noisy version of the original video frames, and a decoder of the error-control code corrects the errors in the side information with the syndrome bits. The noisy observation, i.e., the side information can be understood as the output of a virtual channel corresponding to the orignal video frames, and the conditional probability of the virtual channel model is assumed to follow a Laplacian distribution. Thus, performance improvement of DVC systems depends on performances of the error-control code and the optimal reconstruction step in the DVC decoder. In turn, the performances of two constituent blocks are directly related to a better estimation of the parameter of the correlation channel. In this paper, we propose an algorithm to estimate the parameter of the correlation channel and also a low-complexity version of the proposed algorithm. In particular, the proposed algorithm minimizes squared-error of the Laplacian probability distribution and the empirical observations. Finally, we show that the conventional algorithm can be improved by adopting a confidential window. The proposed algorithm results in PSNR gain up to 1.8 dB and 1.1 dB on Mother and Foreman video sequences, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.1
• /
• pp.170-178
• /
• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.