• Journal of the Korean Vacuum Society
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• v.22 no.6
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• pp.306-312
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• 2013

Single-crystalline InSb nanowire was synthesized on $SiO_2$ wafer via vapor-liquid-solid (VLS) mechanism using chemical vapor deposition method. According to the source container system (open or close) which contain InSb powder and $SiO_2$ wafer, the single-crystalline InSb nanowires have different growth mechanisms. Structural characterization of the InSb nanowires was examined by scanning electron microscope (SEM). Composition of the nanowires was investigated using x-ray diffraction (XRD) and energy dispersive x-ray spectroscopy (EDS). This study demonstrates that length and diameter of the InSb nanowires are long and thick using open-boat system by VLS and additional vapor-solid (VS) mechanisms, because open-boat system can carry a large amount of vapor-phase InSb precursor than close-boat system.

• Korean Journal of Environmental Agriculture
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• v.16 no.2
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• pp.156-160
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• 1997

The combination of biological wastewater treatment process and membrane separation has many advantages such as better effluent quality and system stability over the conventional biological wastewater treatment process. In this study, direct membrane separation using nonwoven fabric was applied to biological wastewater treatment. A nonwoven fabric module was submerged in the aerated bioreactor. And accumulated biomass in the bioreactor was separated by suction. The system was operated with various condition to investigate pollutant removal efficiencies and flux. After formation of biomass layer on nonwoven fabric surface, a day, the stable effluent water quality was obtained. The flux decreased at a high suction pressure faster than a low pressure. The stable flux was obtained at the pressure of $21{\sim}25cmHg$. In spite of variation of hydraulic retention time, organic loading rate, the removal efficiencies of BOD, $COD_{Cr}$. $COD_{Mn}$ were very high as follows : $95.2%(0.14{\sim}0.97\;BODKg/m^3/day)$, $86.0%(0.17{\sim}1.39\;COD_{Cr}Kg/m^3/day)$, $90.0%(0.097{\sim}0.61\;COD_{Mn}Kg/m^3/day)$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1340-1350
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• 2009

The design and implementation of planar Active Phased Array Antenna System are described in this paper. This Antenna system operates at X-band with its bandwidth 10 % and dual polarization is realized using dual slot feeding microstrip patch antenna and SPDT(Single Pole Double Through) switch. Array Structure is $16\times16$ triangular lattice structure and each array is composed of TR(Transmit & Receive) module with more than 40 dBm power. Each TR module includes digital attenuator and phase shifter so that antenna beam can be electronically steered over a scan angle$({\pm}60^{\circ})$. Measurement of antenna pattern is conducted using a near field chamber and the results coincide with the expected beam pattern. From these results, it can be convinced that this antenna can be used with control of beam steering and beam shaping.

• Journal of Korea Multimedia Society
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• v.2 no.2
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• pp.217-229
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• 1999

Framework is the set of interrelated classes, constructing reusable design in specific domain or set of abstracted classes, and defines common architecture among applications included in domain. Developers can reuse not only class code but also wide range of knowledge on domain by reusing framework. In this papers, we present COM(Component-Oriented Methodology) for the reuse of framework, and develop construction environment for framework and domain development. That is, domain is analyzed by input of domain knowledge on real world to create software based on component, and hotspot is identified through analyzed information, and redesigned(refactoring) by putting additional information on users and developers. After that, I will create domain framework and application framework depending on domain. In this Component-oriented methodology, information is searched, understood and extracted or composite through component-pattern library storage internally. Then this information is classified into the information on component and pattern respectively, and used as additional information in redesigning. With this, developer can obtain reusability, easiness and portability by constructing infrastructure environment that allow to register, update and delete component through Component Pattern Management System(CPMS) under the development environment which can be easily applied to his own application using multimedia component, in this thesis, CORBA(Common Object Request Broker Architecture) environment.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.11
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• pp.683-692
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• 2020

A joint displacement resistance evaluation method for selecting waterproofing materials in railway bridge decks is proposed. The displacement range for an evaluation is determined by finite element method (FEM) analysis of a load case based on an existing high-speed PSC Girder Box railroad bridge structure. The FEM analysis results were used to calculate the minimum joint displacement range to be applied during testing (approximately 1.5 mm). For the evaluation, four commonly used waterproofing membrane types, cementitious slurry coating (CSC), polyurethane coating system (PCS), self-adhesive asphalt sheet (SAS), and composite asphalt sheet (CAS), were tested, with five specimens of each membrane type. The joint displacement width range conditions, including the minimum displacement range obtained from FEM analysis, were set to be the incrementing interval, from 1.5, 3.0, 4.5, and 6.0 mm. The proposal for the evaluation criteria and the specimen test results demonstrated how the evaluation method is important for the sustainability of high-speed railway bridges.

• The KIPS Transactions:PartD
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• v.11D no.1
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• pp.133-142
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• 2004

The next generation of web applications will need to be larger, more complex, and flexible Agent-oriented systems have great potential for these e-commerce applications. Agents can dynamically discover and compose e-services and mediate interactions. Development of software agents with CBD (Component Based Development) has proved to be successful in increasing speed to market of development Projects, lowering the development cost and providing better qualify. In this thesis, we propose a systemic development process for software agents using component and UML (Unified Modeling Language). We suggest a etA (e-business Agent) CBD reference architecture for layer the related components through identification and classification of general agent and e-business agent. We also propose the ebA-CBD process that is a guideline to consider the best features of existing agent oriented software engineering methodologies, while grounding agent-oriented concepts in the same underlying semantic framework used by UML. We first developed the agent components specification and modeled it with Goal, Role, Interaction, and Architecture Model. Based on this, we developed e-CPIMAS (e-Commerce Product Information Mailing Agent System) as a case study that provides the product information's mailing service according to proposed process formality. We finally describe how these concepts may assist in increasing the efficiency reusability, productivity and quality to develop the business application and e-business agent.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.9
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• pp.1029-1036
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• 2014

Several types of automatic 3D scanners are available for use in the 3D scanning industry, e.g., an automatic 3D scanner that uses a robot arm and one that uses an automatic rotary table. Specifically, these scanners are used to obtain a 3D shape using automatic assisting devices. Most of these scanners are required to perform numerous operations, such as merging, aligning, trimming, and filling holes. We are interested in developing an automatic 3D shape collection device using a spherical-coordinate-based guiding system. Then, the aim of the present study is to design an automatic guiding system that can automatically collect 3D shape data. We develop a 3D model of this system and measuring data which are collected by a personal computer. An optimal design of this system and the geometrical accuracy of the measured data are both evaluated using 3D modeling software. The developed system is then applied to an object having a highly complex shape and manifold sections. Our simulation results demonstrate that the developed system collects higher-quality 3D data than the conventional method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.12
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• pp.7324-7330
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• 2014

Color distortion of the dark images acquired under a low-light-level environment with a weak light source can be cause of the performance decreation of various vision systems. Therefore, recovering the original color of the images is an important process for enhancing the performance of the system. For this, this study proposes a color restoration method using a dichromatic reflection model. This paper assumes that the dark images can be classified into two parts affected by specular or diffuse reflection. Two different color constancy methods were then applied to the images to remove the effects of each reflection and two images were created as a result. The resulting images produced a one color-corrected image by combining with different weights according to the position in the images. For the performance evaluation, this paper used a synthesized image, and considered the Euclidean distance and angular error as an evaluation factor. In addition, a performance comparison was performed with the existing various color constancy method to achieve the objectivity of evaluation. The experimental results showed that the proposed method can be a more suitable solution for color restoration than the existing method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.