• Korean Journal of Clinical Laboratory Science
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• v.48 no.4
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• pp.348-354
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• 2016

Data stored in hospital information systems has a great potential to improve adequacy assessment and quality management. Moreover, an establishment of a data warehouse has been known to improve quality management and to offer help to clinicians. This study constructed a data mart that can be used to analyze antibiotic usage as a part of systematic and effective data analysis of infection control information. Metadata was designed by using the XML DTD method after selecting components and evaluation measures for infection control. OLAP-a multidimensional analysis tool-for antibiotic usage analysis was developed by building a data mart through modeling. Experimental data were obtained from data on antibiotic usage at a university hospital in Cheonan area for one month in July of 1997. The major components of infection control metadata were antibiotic resistance information, antibiotic usage information, infection information, laboratory test information, patient information, and infection related costs. Among them, a data mart was constructed by designing a database to apply antibiotic usage information to a star schema. In addition, OLAP was demonstrated by calculating the statistics of antibiotic usage for one month. This study reports the development of a data mart on antibiotic usage for infection control through the implementation of XML and OLAP techniques. Building a conceptual, structured data mart would allow for a rapid delivery and diverse analysis of infection control information.

• The KIPS Transactions:PartB
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• v.9B no.4
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• pp.399-406
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• 2002

The goal of this research has been to develop an adaptive user agent for web surfing. To achieve this goal, the research has concentrated on three issues: collection of user data, construction and improvement of user profile, and adaptation by applying the user profile. The main outcome from the research is a prototype system that provides the functional definition and componential design scheme for an adaptive user agent for the web environment. Internally, the system achieves its operational goal from the cooperation of two independent agents. They are IIA (Interactive Interface Agent) and UPA (User Profiling Agent). As a tool for providing a user-friendly interface environment, the IIA employs the Keyword Index, which is a list of index terms of a webpage as well as a keyword menu for subsequent queries, and the Suggest Link, which is a hierarchical list of URLs showing the past browsing procedure of the user. The UPA reflects in the User Profile, both the static and the dynamic information obtained from the user's browsing behavior. In particular, a user's interests are represented in the form of Interest Vectors which, based on the similarity of the vectors, is subject to update and creation, thus dynamically profiling the user's ever-shifting interests.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.490-496
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• 2007

This paper describes the design and implementation of an integrated LTCC front-end module for the IEEE802.11a WLAN applications by performing the behavioral-level simulation using measurement-based behavioral model. To meet the IEEE802.11a WLAN standard, a system transmitting 1024 symbols through 64-QAM process at the rate of 54Mbps should be implemented and nonlinear properties are confirmed by simulations of ACPR and EVM in this circumstance. The right offsets of ACPR which are 30MHz, 20MHz, and 11MHz distant from the center frequency of 5.8GHz are 49.36dBc, 36.90dBc, and 24.58dBc, respectively. The left offsets are 50.14dBc, 30.04dBc, and 28.85dBc, respectively and EVM is 2.94%. The size of the module implemented with LTCC five-layer substrates is $13.4mm{\times}14.2mm$. The measured characteristics of the transmitter show P1dB of 16.2dBm and power gain of 16.73dB. Those of the receiver exhibit the small signal gain of 16.24dB and noise figure of 7.83dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.181-187
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• 2020

In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.

• The KIPS Transactions:PartB
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• v.13B no.1 s.104
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• pp.63-70
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• 2006

In general, a corpus contains lots of linguistic information and is widely used in the field of natural language processing and computational linguistics. The creation of such the corpus, however, is an expensive, labor-intensive and time-consuming work. To alleviate this problem, annotation tools to build corpora with much linguistic information is indispensable. In this paper, we design and implement an annotation tool for establishing a Korean dependency tree-tagged corpus. The most ideal way is to fully automatically create the corpus without annotators' interventions, but as a matter of fact, it is impossible. The proposed tool is semi-automatic like most other annotation tools and is designed to edit errors, which are generated by basic analyzers like part-of-speech tagger and (partial) parser. We also design it to avoid repetitive works while editing the errors and to use it easily and friendly. Using the proposed annotation tool, 10,000 Korean sentences containing over 20 words are annotated with dependency structures. For 2 months, eight annotators have worked every 4 hours a day. We are confident that we can have accurate and consistent annotations as well as reduced labor and time.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.209-218
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• 2012

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• Journal of the Korea Society of Computer and Information
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• v.16 no.12
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• pp.1-10
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• 2011

As requirements of embedded system get complicated, the tool for analyzing the reliability of embedded software is being needed. A probabilistic modeling is used as the way of analyzing the reliability of a software and to apply it to embedded software controlling multiple devices. So, it is necessary to specialize that to embedded software. Also, existing reliability analyzers should measure the transition probability of each condition in different ways and doesn't consider reusing the model once used. In this paper, we suggest a reliability analyzer for embedded software using embedded software Markov chin model and a unit testing tool. Embedded software Markov chain model is model specializing Markov chain model which is used for analyzing reliability to an embedded software. And a unit testing tool has host-target structure which is appropriate to development environment of embedded software. This tool can analyze the reliability more easily than existing tool by automatically measuring the transition probability between units for analyzing reliability from the result of unit testing. It can also directly apply the test result updated by unit testing tool by representing software model as a XML oriented document and has the advantage that many developers can access easily using the web oriented interface and SVN store. In this paper, we show reliability analyzing of a example by so doing show usefulness of reliability analyzer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.758-765
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• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2223-2231
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• 2015

In this paper, we propose a built-in antenna for wireless USB dongle which has a modified structure from the existing planar monopole antenna. The proposed antenna implemented a dual-band characteristic by inserting Strip1, Strip2, Strip3 into the monopole structure combined with 'n' shape and feeded 50-Ω using coaxial cable. The antenna is designed on an FR-4 substrate of which the dielectric constant is 4.6, and its overall size is 10 mm × 50 mm × 1mm. Based on the measurement results of the return loss, it was confirmed to satisfy the dual band resonance characteristics of 740 MHz (2.3 ~ 2.7 GHz) and 1,200 MHz (5.15 ~ 5.825 GHz) by -10 dB. In addition, we obtain the omni-directional radiation pattern measurements in the operating frequency bands, and the maximum gain of the proposed antenna has 2.26~3.81 dBi in the 2.4 GHz band and 2.21~5.79 dBi. in the 5.5 GHz band, respectively.