• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.80-89
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• 2006

The rapid development of process technology and the introduction of new materials not only make it difficult for process control but also as a result increase process variations. These process variations are barriers to successful implementation of design circuits because there are disparities between data on layout and that on wafer. This paper proposes a new design environment to determine the interconnect worstcase with accuracy and speed so that the interconnect effects due to process-induced variations can be applied to designs of $0.13{\mu}m$ and below. Common Geometry and Maximum Probability methods have been developed and integrated into the new worstcase optimization algorithm. The delay time of the 31-stage Ring Oscillator, manufactured in UMC $0.13{\mu}m$ Logic, was measured, and the results proved the accuracy of the algorithm. When the algorithm was used to optimize worstcase determination, the relative error was less than 1.00%, two times more accurate than the conventional methods. Furthermore, the new worstcase design environment improved optimization speed by 32.01% compared to that of conventional worstcase optimizers. Moreover, the new worstcitse design environment accurately predicted the worstcase of non-normal distribution which conventional methods cannot do well.