• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.553-563
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• 2010

This paper presents a tapered slot-antenna(TSA) for optimal impulse-signal transmission in ultra-wide band(UWB). The proposed TSA provides radiates in end-fire direction, which meets an impulse-radio UWB(IR-UWB) system demands(e.g., low loss, thus less error throughout the UWB band). In order to minimize the pulse distortion, we used an wideband impedance transformer and a microstrip slotline. The pulse fidelity characteristics was evaluated with finite-difference time-domain(FDTD) analysis technique and pulse fidelity correlation equation. Approximately 93.89 % pulse fidelity was obtained between the two antennas in 0.5 m range. Additionally, derived chirp Z-transform algorithm enables us to utilize the zoom-in option on the pulse signal in few nano-seconds below. Thus, it is possible to analyze the pulse signal distortion, delay or dispersion characteristics.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.4
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• pp.25-40
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• 2012

This paper suggests the way to build the integration of internal server by using link server with virtualization method. With the development of on-line games, game communities began to be formed by users, players get fun from playing games, sharing online space with friends, clans, and parties. However, the limit of physical server restrict the allows under average a hundred users to play at same time and place, and three thousand to ten thousand people to access to game community with chat, message, friends functions. By following the explanation of the method from this paper, this limit can be overcome. It will give the function to share information of all connected users in one displayed server. This paper demonstrates the key quality requirements of the server built by this way such as scalable architecture, consistency, and latency is fulfilled.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.12 s.177
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• pp.51-60
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• 2005

This paper describes a robust control scheme for high-speed and long stroke scanning motion of high precision linear motor system consisting of linear motor, air bearing guide and position measurement system using heterodyne interferometer. Nowadays, semiconductor process and inspection of wafer or LCD need high speed and long travel length for their high throughput and extremely small velocity fluctuations or tracking errors. In order to satisfy these conditions, linear motor system are widely used because they have large thrust force and do not need motion conversion mechanisms such as ball screw, rack & pinion or capstan with which the system are burdened. However linear motors have a problem called force ripple. Force ripple deteriorates the tracking performances and makes periodic position errors. So, force ripple must be compensated. To maximize the tracking performance of linear motor system, we propose the control scheme which is composed of a robust control method, Time Delay Controller (TDC) and a feedforward control method, Zero Phase Error Tracking Control (ZPETC) for accurate tracking a given trajectory and an adaptive force ripple compensation (AFC) algorithm fur estimating and compensating force ripple. The adaptive ripple compensation is continuously refined on the basis of tracking error. Computer simulation results based on modeled parameters verify the effectiveness of the proposed control scheme for high-speed, long stroke and high precision scanning motion and show that the proposed control scheme can achieve a sup error tracking performance in comparison to conventional TDC control.

• Journal of the Korean Professional Engineers Association
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• v.19 no.2
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• pp.10-20
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• 1986

This paper describes a countermeasure of electric utilities and customer equipment in order to minimize an effect of sensitive electrical and electronic equipment on the voltage disturbances. After being studied, some schemes to solve were discovered. Firstly, in the electric utilities, the reduction of frequency and influence of voltage drop's time are not easy to realize because of the standpoint of effect and economy. Secondly, in the customer equipment, there are some equipment to minimize the voltage disturbances, Such as an UPSs, a noise suppressors and a power conditioners. One of them should be established on the computer control and automated systems, the electromagnetic switch of delay-release type should be adopted on the electromagnetic switch, the controlling circuit should be adopted on the variable speed motors which is being considered a countermeasure for a momentary under-voltage drops, the luminaire adhering a instantaneous restrike device should be adopted on the HID lamp. And also, the scheme of extending a setting time of relay on the undervoltage relay and the forming method of sequence which is automatic reclosing at this time of instantaneous suspension of an electric supply have been studied.

• Journal of Advanced Navigation Technology
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• v.19 no.6
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• pp.473-483
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• 2015

This paper reports the single-input-single-output cascade control by using 1-axis attitude control test-bench for quad-rotor UAV. The test-bench was designed as a see-saw shape using 2 motors and propellers, and to enable changing the center of gravity with the center of gyration using ballast. The experiment was carried out by constructing a PID-PID controller having a cascade structure with the test-bench. The SIMC based PID gain tuning process, which makes PID gain tuning easy, was grafted to cascade control. To graft SIMC method, the system parameter estimation result was conducted with second order time delay model by using Matlab-Simulink. Gain tuning was conducted by simulating with estimated system parameter. In this paper, the conventional application of SIMC was conducted and improved application was proposed for improving stability at tuning process.

• KIISE Transactions on Computing Practices
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• v.23 no.7
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• pp.428-433
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• 2017

Recently, the demand for high performance non-volatile memory storage devices that can replace existing hard disks has been increasing in environments requiring high performance computing such as data-centers and social network services. The performance of such non-volatile memory can greatly depend on the interface between the host and the storage device. With the evolution of storage interfaces, the non-volatile memory express (NVMe) interface has emerged, which can replace serial attached SCSI and serial ATA (SAS/SATA) interfaces based on existing hard disks. The NVMe interface has a higher level of scalability and provides lower latency than traditional interfaces. In this paper, an evaluation and analysis are conducted of the performance of NVMe storage devices through various workloads. We also compare and evaluate the cost efficiency of NVMe SSD and SATA SSD.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1435-1440
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• 2017

Recently, VR and AR are emerging as an area of interest in ICT. In virtual reality to feel like a real, many people are looking for them because of its charm. However, the motion of the VR image and the moving object are not synchronized exactly, and a problem of feeling nausea is also occurring. The problem should be solved by the application of Attraction in the VR system. In this paper, we propose a module that minimizes delay time by synchronizing movement of VR image and moving object. The proposed module calculates the moving distance using the direction and the acceleration sensor that the user views through the VR device. The module proposed in this paper will pay attention to the fact that the movement of the attraction moves along a fixed path, so that the accurate travel distance can be calculated.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• The KIPS Transactions:PartC
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• v.17C no.3
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• pp.243-250
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• 2010

Vehicular communication networking is one of the most important building blocks of Intelligent Transportation System (ITS). The vehicular communication network is a wireless communication system enabling vehicles to communicate with each other as well as with roadside base stations. Mobility management of vehicles which move at high speeds and occasionally make a long journey is an interesting research area of vehicular communication networks. Recently, The Proxy Mobile IPv6 (PMIPv6) protocol is proposed for network-based mobility management to reduce the overhead of mobile nodes. PMIPv6 shifts the burden of the mobility management from mobile nodes to network agents to decrease the overhead and latency for the mobility management. In this paper, we derive the scenario of deploying PMIPv6 in vehicular communication networks and propose a new LMA handover mechanism for realizing the scenario. By carrying out the ns-2 based simulations, we verify the operability of the proposed mechanism.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.101-108
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• 2000

The data prefetching scheme is an effective technique to reduce the main memory access latency by exploiting the overlap of processor computations with data accesses. However, if the prefetched data replicate the useful existing data in the cache memory and they are not being used in computations. performances of programs are aggravated. This phenomenon results from the lack of correct predictions for data being used in the future. When parallel programs exploit the data arrays for computations, the grain size is useful information for data prefetching scheme because it implies the range of data using in computations. Based on this information, we suggest a new data prefetching scheme exploited by the grain size of the parallel program. Simulation results show that the suggested prefetching scheme improves the performance of the simulated parallel programs due to the reduction of bus transactions as well as useful prefetching operations.