• Journal of Digital Convergence
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• v.12 no.9
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• pp.201-207
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• 2014

In the cloud environment, the company needs data integration and analysis to make decision and policy. If new system is added to this environment, a lot of time and cost is needed due to disparate properties among systems when data is integrated. Therefore, in this paper, we propose a DBaaS hub system for multi-database service. The DBaaS may require a different database and need data integration for relevant service. Using the ontology, we propose a metadata query to resolve the interoperability issues between data of DBaaS. The meta-query is not a query to access the real data, but the query for the upper level. This method provides data integration by accessing the data with the converted query through an ontology when we access the actual database.We also constructs a document-oriented database system using the metadata.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.31 no.2
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• pp.159-164
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• 2013

It is well known that a single moving camera video is capable of extracting the 3-dimensional position of an object. With this in mind, current research performed image-based monitoring to establish a floating structure model using a camcorder system. Following this, the present study extracted frame images from digital camcorder video clips and matched the interest points to obtain relative 3D coordinates for both regular and irregular wave conditions. Then, the researchers evaluated the transformation accuracy of the modified SURF-based matching and image-based displacement estimation of the floating structure model in regular wave condition. For the regular wave condition, the wave generator's setting value was 3.0 sec and the cycle of the image-based displacement result was 2.993 sec. Taking into account mechanical error, these values can be considered as very similar. In terms of visual inspection, the researchers observed the shape of a regular wave in the 3-dimensional and 1-dimensional figures through the projection on X Y Z axis. In conclusion, it was possible to calculate the displacement of a floating structure module in near real-time using an average digital camcorder with 30fps video.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.10
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• pp.185-190
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• 2007

In this paper, minimum sampling rates and method of nonlinear characterization were suggested for low power, quasi-memoryless PAs. So far, the Nyquist rate of the input signal has been used for nonlinear PA modeling, and it is burdening Analog-to-digital converters for wideband signals. This paper shows that the input Nyquist rate sampling is not a necessary condition for successful modeling of quasi-memoryless PAs. Since this sampling requirement relives the bandwidth requirements for Analog-to-digital converters (ADCs) for feedback paths in digital pre-distortion systems, relatively low-cost ADcs can be used to identify nonlinear PAs for wideband signal transmission, even at severe aliasing conditions. Simulation results show that a generic memoryless nonlinear RF power amplifier with AMAM and AMPM distortion can be successfully identified at any sampling rates. Measurement results show the modeling error variation is less than 0.8dB over any sampling rates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• The Journal of the Acoustical Society of Korea
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• v.8 no.1
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• pp.5-12
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• 1989

This paper is concerned with the characteristics on the statistical parameters of vibration signal from bearing with changing its operating conditions as well as the spreading of faults. The rms, Kurtosis, crest factor, probability of exceedance and probability density function have been chose as the statistical parameters. To characterize of each, vibration signals have been recorded from four ball tester at different loads, operation speeds and time. The values of the statistical parameters for each frequency band have been calculated after A/D conversion and digital filtering of the recorded signals. It has been found that unlike rms values the statistical parameters such as Kurtosis etc. are almost unchanging with the change of the operating conditions such as load and speed. This suggests that the statistical parameters may be used for determining the development of faults independent of the operating conditions. In fact, the statistical parameters deviate considerably from their respective normal values when the faults developed under load conditions in the samples, conforming the suggestion.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.5
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• pp.558-565
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• 2013

In this paper, modeling and simulation for performance analysis of high resolution SAR system has been carried out in the time, frequency and numeric domain using ADS Ptolemy simulation tool of Agilent corporation. SAR system consists of antenna, controller and transceiver. Error parameters affecting SAR system performances have been defined, modeled and simulated such as phase noise of frequency synthesizer, amplitude and phase characteristic of TWTA, sampling frequency of waveform generator and I/Q imbalance. Finally, the development requirements of SAR system based on the impulse response function have been derived.

• Journal of the Korean Society for Nondestructive Testing
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• v.30 no.2
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• pp.155-161
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• 2010

Recently, the electromagnetic techniques of the eddy current testing(ECT), alternating current field testing, magnetic flux leakage testing and remote field testing have been used as a nondestructive evaluation method based on the electromagnetic induction. The eddy current testing is now widely accepted as a NDE method for the heat exchanger tube in the electric power industry, chemical, shipbuilding, and military. The ECT system mainly consists of the synthesizer module, analog module, analog-to-digital converter, power supplier, and data acquisition and analysis program. In this study, the synthesizer module and the analog module which are essential to the ECT system were primarily developed. The developed ECT system is basically a multifrequency type which is able to inject the maximum four frequencies based on the frequency and time domain multiplexing method. Conclusively, we confirmed that the EC signal was processed appropriately in each circuit modules, and the Lissajous EC signal was displayed in the impedance plane.

• Journal of the Korea Society of Computer and Information
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• v.14 no.2
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• pp.9-16
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• 2009

While the broadband network and multimedia technology are being developed, the commercial market of digital contents as well as using IPTV has been widely spreading. In this background, Time-Shift system is developed for requirement of multimedia. This system is independent of Time but is not independent of Place and Occasion. For solving these problems, in this paper, we propose the TPO(Time, Place, Occasion)-Shift system for mobile multimedia devices. The profile that can be applied to the mobile multimedia devices is much different from that of the setter-box. And general mobile multimedia devices could not have such large memories that is for multimedia data. So it is important to continuously store and manage those multimedia data in limited capacity with mobile device's profile. Therefore we compose the basket in a way using defined time unit and manage these baskets for effective buffer management. In addition. since the file name of basket is made up to include a basket's time information, we can make use of this time information as DTS(Decoding Time Stamp). When some multimedia content is converted to be available for portable multimedia devices, we are able to compose new formatted contents using such DTS information. Using basket based buffer systems, we can compose the contents by real time in mobile multimedia devices and save some memory. In order to see the system's real-time operation and performance, we implemented the proposed TPO-Shift system on the basis of mobile device, MS340. And setter-box are desisted by using directshow player under Windows Vista environment. As a result, we can find the usefulness and real-time operation of the proposed systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).