• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.529-531
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• 2011

In Gen-2 Q-algorithm, the values of weight C, which is the parameter for incrementing or decrementing the slot-count size, are not defined in the standard. In this case, if the reader selects an inappropriate weight, there are a lot of empty or collided slots. As a result, the performance will be degraded because the frame size does not converge to the optimal point quickly during the query round. In this paper, we analyze how the performances of Gen-2 Q-algorithm will be affected by the weight value.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.9-18
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• 2004

The IEEE 802.11 Distributed Coordination Function(DCF) protocol provides a contention-based distribution channel access mechanism for stations to share the wireless medium. However, the performance of the DCF drops dramatically in terms of throughput, delay and delay jitter as the number of active stations becomes large. In this paper, we propose a simple and effective scheme, called DCF/VG(Distributed Coordination Function with Virtual Group), for improving the performance of the IEEE 802.11 DCF mechanism. In this scheme, each station independently decides the virtual group cycle using the information provided by the carrier sensing mechanism. The virtual group cycle consists of one or more virtual groups and a virtual group includes an idle period and a busy period. Each station operates in only one out of several virtual groups of the virtual group cycle and does not operate in the others. In other words, each station decreases its backoff counter and tries to transmit a packet only in its virtual group like the IEEE 802.11 DCF. Performance of the proposed scheme is investigated by numerical analysis and simulation. Numerical and simulation results show that the proposed scheme is very effective and has high throughput and low delay and jitter under a wide range of contention level.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.379-388
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• 1998

In this paper we propose a DMR-II shared-medium access control protocol which was developed for the ATM access network users to support isochronous and non-isochronous traffics simultaneously under the bandwidth sharing environment, and describe its architecture and operation principles. The DMR-II protocol uses the slotted-ring topology, and gives the higher transmission priority to the isochronous traffic than the non-isochronous traffic. To support the isochronous traffic it uses the slot reservation mechanism, and maintains the delay variation of the isochronous traffic beyond the threshold value by using the blocking mechanism whenever the total user traffic overflows the network's bandwidth limitation. for the non-isochronous traffic the DMR-II protocol lets all the nodes to have fair transmission chances by using the reset mechanism based on the window counter scheme.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.5
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• pp.33-39
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• 2010

In this paper, we propose an improved anti-collision algorithm. We have designed an anti-collision unit using this algorithm for the 18000-6 Type C Class 1 Generation 2 standard (Gen2). The Gen2 standard uses a Q-algorithm for incremental method on the Dynamic Slot-Aloha algorithm. It has basically enhanced performance over the Slot-Aloha algorithm. Unfortunately, there are several non-clarified parts: initial value. If an incorrect value is selected, it causes degradation in performance. To increase throughput and system efficiency, and to decrease tag identification time, we propose an improved anti-collision algorithm. prorosed Q algorithm has an increment of 5% of system efficiency and a decrement of 9% of tag identification time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.310-317
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• 1993

This paper presents a mechanism for improving performance of the IEEE 802.6 MAN(Metropolitan Area Network), a dual-bus structured high-speed communication network, by a more efficient use of bandwidth. The MAN protocol is able to handle various traffic and offers better transmission speed than the conventional LAN, but the unidirectional bus structure and propagation delay of request bits results in unfairness since higher nodes use more bandwidth. As the number of stations and the distances between them are increased, the problem becomes mere serious. As a solution, this paper presents a method that every station enables to identify the used slots, and that a specified class denoted 'erasure station' has with the functions of destination release, slot reuse. As a result, it is export to improve network bandwidth values of each station and the throughput and delay time was analytically analyzed, and it is shown that according to computer simulation results, this mechanism improves the network performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2A
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• pp.177-183
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• 2009

In this paper, we propose an improved anti-collision algorithm. We have designed an anti-collision unit using this algorithm for the 18000-6 Type C Class 1 Generation 2 standard (Gen2). The Gen2 standard uses a Q-algorithm for incremental method on the Dynamic Slot-Aloha algorithm. It has basically enhanced performance over the Slot-Aloha algorithm. Unfortunately, there are several non-clarified parts: initial $Q_{fp}$ value, weighted C, and the ending point of the algorithm. If an incorrect value is selected, it causes degradation in performance. Thus we propose an improved anti-collision algorithm by clearly defining the vague parts of the existing algorithm. Simulation results showed an improved performance of up to 34.8% using an optimized value of C and the initial $Q_{fp}$ value. With the ending condition, performance is 34.7%. The anti-collision unit is designed using the Verilog HDL. The module was synthesized using Synopsys' Design Compiler and the TSMC $0.2{\mu}m$ standard cell library. The synthesized result yielded 3,847 gates, and was guaranteed under the proposed working frequency of 19.2MHz.