• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.80-86
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• 2006

In this paper, we propose the PingPong-128(PP-128) keystream generator, based on summation generator. Proposed PingPong-128, a specific cipher of the PingPong Family, takes 128 bits key and 128 bit initial vector, has 258 bit internal state, and achieves a security level of 128 bits. The security analysis of PingPong-128 is presented, including the resistence to known attacks against the summation generator and other clock-controlled generators.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2113-2120
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• 2009

User authentication has been one of the most important part of the network system. OTP(One-Time Password) has been developed and applied to the existing authentication system. OTP makes a different password and abrogates used password each time when user is authenticated by the server. Those systems prevent stolen-key-problems which is caused by using the same key every log-in trial. Yet, OTP still has vulnerabilities. In this paper, an advanced protocol which is using clock-count method to apply a stream cipher algorithm to OTP protocols and to solve problems of existing OTP protocols is proposed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.326-329
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• 2017

Most modern computer communications and storage media support encryption technology. Many of the Ping Pong algorithms are stream ciphers that generate random numbers in the LFSR core structure. The LFSR has a structure that guarantees the maximum period of a given size, but it has a linear structure and can be predicted. Therefore, the Ping Pong algorithm has a feature of making the linearity of the LFSR into a nonlinear structure through variable clocks and functions. In this paper, we try to improve the existing linearity by replacing the linear disadvantages of LFSR with logistic maps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.5
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• pp.17-24
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• 2009

Zhang et al. proposed a improved fast correlation attack on stream ciphers at SAC'08[8]. This attack is based on the fast correlation attack proposed at Crypto'00 and combined with FWT(fast Walsh transform). Given various attack environments, they presented complexities and success probabilities of the proposed attack algorithm. However, we found that our simulation results of the proposed attack algorithm are different from them presented in [8]. In this paper, we correct results of the proposed attack algorithm by analyzing it theoretically. And we propose a threshold of valid bias.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.6
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• pp.111-117
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• 2005

The period of a recent streamcipher proposal Edon80 is analyzed. The designers of Edon80 had projected a period of $2^{103}$ Even though this could indeed be the average keystream Period, we show that for a randomly chosen key-IV pair, there exists a non-dismissible probability that the produced keystream will be of relatively short period. More explicitly, a keystream of period. $2^{55}$ may appear with probability $2^{-71}$, and one can show the existence of at least one key-lV pair producing a period $2^{11}$ keystream.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.1
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• pp.3-10
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• 2012

In this paper, we propose a fault injection attack on stream cipher A5/3 used in GSM. The fault assumption of this attack is based on that of fault injection attacks proposed in FDTC'05 and CISC-W'10. This attack is applicable to A5/3 supporting 64/128-bit session key, respectively, and can recover the session key by using a small number of fault injections. These works are the first known key recovery attack results on A5/3.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.18-24
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• 2004

Nowadays, the development of wireless communications provides a convenience for many people. On the other hand, the openness of wireless communications poses serious security threats and the security of wireless communications is necessary to support the secure communication channel. The common security method on wireless is the stream cipher that generates the pseudorandom number. In this paper, we propose the usage of the nonlinear function S-box and the mechanism according to it in stream cipher as the study to securely protect data transferred on wireless communications. Besides, it goes abreast a study on S-box with the best random characteristic among the used S-boxes on wireless communications. By means of test, we investigate the most appropriate S-box of DES on wireless communications environment and prove the efficiency of the proposed model by comparing and analysis of the randomness of the based stream cipher and the proposed model.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.89-95
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• 2007

There are various methods constructing correlation immune functions such as Siegenthaler's, Camion et al's and Seberry et al's. In particular, Soberry et al's is a method which directly constructs balanced correlation immune functions of any order using the theory of Hadamard matrices. In this paper, we have studied Seberry et al's method for constructing a correlation immune function on a higher dimensional space by combining known correlation immune functions on a lower dimensional space. Futhermore, we calculated the nonlinearity of functions which are constructed by combining of several correlation immune functions. That is, we have shown that the direct sum of two correlation immune functions and a combination of four correlation immune functions have higher nonlinearity in comparison with each functions. This functions in stream cipher are safe against correlation attacks.

• Convergence Security Journal
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• v.12 no.4
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• pp.17-23
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• 2012

Recently, the research for cryptographic algorithm, in particular, a stream cipher has been actively conducted for wireless devices as growing use of wireless devices such as smartphone and tablet. LFSR based random number generator is widely used in stream cipher since it has simple architecture and it operates very fast. However, the conventional multi-LFSR RNG (random number generator) suffers from its hardware complexity as well as very closed correlation between the numbers generated. A leap-ahead LFSR was presented to solve these problems. However, it has another disadvantage that the maximum period of the generated random numbers are significantly decreased according to the relationship between the number of the stages of the LFSR and the number of the output bits of the RNG. This paper presents new leap-ahead LFSR architecture to prevent this decrease in the maximum period by applying segmentation technique to the conventional leap-ahead LFSR. The proposed architecture is implemented using VHDL and it is simulated in FPGA using Xilinx ISE 10.1, with a device Virtex 4, XC4VLX15. From the simulation results, the proposed architecture has only 20% hardware complexity but it can increases the maximum period of the generated random numbers by 40% compared to the conventional Leap-ahead archtecture.