• Proceedings of the Korea Inteligent Information System Society Conference
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• 1999.03a
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• pp.195-202
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• 1999

본 논문은 배전 계통에서 부하 제약조건과 운전 제약조건을 고려한 손실 감소와 부하 평형에 대해 시뮬레이티드 어닐링 알고리즘을 적용한 재구성 방법을 서술하였다. 네트워크 재구성은 수많은 연계 개폐기와 구분 계폐기의 조합에 의해 이루어지기 때문에 조합적인 최적화 문제이다. 이러한 문제는 수많은 조합에 제약조건까지 있어 해를 구하기가 쉽지 않을뿐 아니라 국소 해에 빠질 가능성이 많다. 따라서 신경망 중에서 제약조건에 따라 신경망 구조에 영향을 미치지 않으면서 전역 최소해에 수렴하는 특성을 가진 시뮬레이티드 어닐링 기법을 이용하여 배전 계통의 선로를 재구성하였다. 시뮬레이티드 어닐링은 이론적으로 최적해가 보장되지만 무한대의 시간이 걸리기 때문에 현실적으로 적용할 때 해 공간을 탐색하는 규칙과 온도를 적절히 내리는 냉각 스케줄(cooling schedule)이 중요하다. 본 논문에서는 알고리즘 상에서 제약조건 위한 여부를 점검할 수 있는 제약조건과 페널티 상수(penalty factor)를 통해 목적함수에 반영하는 제약조건으로 나누어 모든 후보해를 가능해가 되게 하였고 기존에 사용되는 Kirkpatrick의 냉각 스케줄 대신에 후보해의 통계적 처리에 의해 온도를 내리는 다항-시간 냉각 스케줄(polynomial-time schedule)을 사용하여 수행시간을 단축하고 수렴성을 높였다. 제안한 알고리즘의 효용성을 입증하기 위해 32,69모선 예제 계통으로 테스트하였다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2011.06a
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• pp.129-132
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• 2011

본 논문은 사진의 메타정보에 저장되어 있는 GPS(Global positioning system)데이터를 추출하여 사진을 이용하여 데이터베이스를 연동한 정보를 통하여 장소에 대한 스케줄러 시스템 구현에 대한 논문이다. 연구를 위하여 웹 시스템 상에서 사진파일에 저장되어 있는 GPS데이터 추출하는 방법과 다수의 사진을 선택하여 스케줄링 하는 시스템 구현에 중점을 다루였다. 특히 스케줄링 방법에 있어서 위치정보가 포함되어 있는 사진파일을 다수 선택을 하였을 경우 위치정보에 따라 최적화된 최단거리 최적 시스템을 구축하였으며, 이렇게 구축된 정보를 데이터베이스에 포함을 시키고, 데이터베이스를 이용하여 전자지도와의 연동을 통해 보다 쉽고 편리하게 확인할 수 있도록 구현하였다. 본 시스템은 추후 여행사의 사이트 혹은 위치정보가 사용되는 다양한 서비스분야로 활용 할 수 있을 것이다.

• Journal of Internet Computing and Services
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• v.6 no.6
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• pp.99-106
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• 2005

The task scheduling in multiprocessor system Is one of the key elements in the effective utilization of multiprocessor systems. The optimal assignment of tasks to multiprocessor is, in almost all practical cases, an NP hard problem. Consequently various modern heuristics based algorithms have been proposed for practical reason. Recently, several approaches using Genetic Algorithm (GA) are proposed. However, these algorithms have only one objective such as minimizing cost and makespan. This paper proposes a new task scheduling algorithm using Genetic Algorithm combined simulated annealing (GA+SA) on multiprocessor environment. In solution algorithms, the Genetic Algorithm (GA) and the simulated annealing (SA) are cooperatively used. In this method. the convergence of GA is improved by introducing the probability of SA as the criterion for acceptance of new trial solution. The objective of proposed scheduling algorithm is to minimize makespan and total number of processors used. The effectiveness of the proposed algorithm is shown through simulation studies. In simulation studies, the results of proposed algorithm show better than that of other algorithms.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.968-972
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• 2009

The multi-core processors are being widely exploited by many high-end systems. With significant advances in processor architecture, the network band-width required on the high-end systems is increasing drastically. It is therefore highly desirable to manage multiple cores efficiently to achieve high network band-width with minimum resource requirements. Modern operating systems, however, still have significant design and optimization space to leverage the network performance over multi-core systems. In this paper, we suggest a novel networking process scheduling scheme, which decides the best processor affinity of networking processes based on the processor cache layout, communication intensiveness, and processor loads. The experimental results show that the scheduling scheme implemented in the Linux kernel can improve the network bandwidth and the effectiveness of processor utilization by 20% and 59%, respectively.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1172-1184
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• 1998

ILP(Instruction Level Parallelism) processors use code reordering algorithms to expose parallelism in a given sequential program. When applied to a loop, this algorithm produces a software-pipelined loop. In a software-pipelined loop, each iteration contains a sequence of parallel instructions that are composed of data-independent instructions collected across from several iterations. For vector loops, however the software pipelining technique can not expose the maximum parallelism because it schedules the program based only on data-dependencies. This paper proposes to schedule differently for vector loops. We develop an algorithm to detect vector loops at object code level and suggest a new vector scheduling algorithm for them. Our vector scheduling improves the performance because it can schedule not only based on data-dependencies but on loop structure or iteration conditions at the object code level. We compare the resulting schedules with those by software-pipelining techniques in the aspect of performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1A
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• pp.76-83
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• 2009

In this paper, we provide opportunistic scheduling schemes for elastic services in OFDMA systems with fairness constraints for each user. We adopt the network utility maximization framework in which a utility function is defined for each user to represent its level of satisfaction to the service. Since we consider elastic services whose degree of satisfaction depends on its average data rate, we define the utility function of each user as a function of its average data rate. In addition, for fair resource allocation among users, we define fairness requirements of each user by using utility functions. We first formulate an optimization problem for each fairness requirement that aim at maximizing network utility, which is defined as the sum of utilities of users. We then develop an opportunistic scheduling scheme for each fairness requirement by solving the problem using a dual approach and a stochastic sub-gradient algorithm.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.10
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• pp.221-230
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• 2020

Supercomputer that shares limited resources to multiple users needs a way to optimize the execution of application. For this, it is useful for system administrators to get prior information and hint about the applications to be executed. In most high-performance computing system operations, system administrators strive to increase system productivity by receiving information about execution duration and resource requirements from users when executing tasks. They are also using profiling techniques that generates the necessary information using statistics such as system usage to increase system utilization. In a previous study, we have proposed a scheduling optimization technique by developing a hardware performance counter-based profiling technique that enables characterization of applications without further understanding of the source code. In this paper, we constructed a profiling testbed cluster to support optimal execution of the supercomputer and experimented with the scalability of the profiling method to analyze application characteristics in the built cluster environment. Also, we experimented that the profiling method can be utilized in actual scheduling optimization with scalability even if the application class is reduced or the number of nodes for profiling is minimized. Even though the number of nodes used for profiling was reduced to 1/4, the execution time of the application increased by 1.08% compared to profiling using all nodes, and the scheduling optimization performance improved by up to 37% compared to sequential execution. In addition, profiling by reducing the size of the problem resulted in a quarter of the cost of collecting profiling data and a performance improvement of up to 35%.

• The Journal of the Korea Contents Association
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• v.7 no.12
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• pp.262-272
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• 2007

SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.4
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• pp.71-81
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• 2010

In grid system, Task scheduling based on list scheduling models has showed low complexity and high efficiency in fully connected processor set environment. However, earlier schemes did not consider sufficiently the communication cost among tasks and the composition process of lightpath for communication in optical gird environment. In this thesis, we propose LSOG (Leveling Selection in Optical Grid) which sets task priority after forming a hierarchical directed acyclic graph (DAG) that is optimized in optical grid environment. To determine priorities of task assignment in the same level, proposed algorithm executes the task with biggest communication cost between itself and its predecessor. Then, it considers the shortest route for communication between tasks. This process improves communication cost in scheduling process through optimizing link resource usage in optical grid environment. We compared LSOG algorithm with conventional ELSA (Extended List Scheduling Algorithm) and SCP (Scheduled Critical Path) algorithm. We could see the enhancement in overall scheduling performance through increment in CCR value and smoothing network environment.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.