• Journal of the Korean Applied Science and Technology
• /
• v.34 no.4
• /
• pp.717-726
• /
• 2017

The current allowable cross-contamination level of fatty acid methyl esters (FAME) in aviation turbine fuel (AVTUR) is 50 mg/kg, due to that the presence of FAME in AVTUR can significantly impact the fuel supply system and jet engine. It has been difficult to analyze the level of FAME in AVTUR, since it is consisted of a lot of hydrocarbons. In this study, thus, a new method using multi-dimensional GC-MS (MDGC-MS) was proposed in order to determine the FAME level in AVTUR effectively. Applying to MDGC-MS with Deans switching system enabled us to detect and quantify the FAME with low carbon numbers such as those derived from coconut oil and palm kernel oil. The matrix effect of MDGC-MS method, which could shift the FAME peaks to slightly longer retention times, was reduced by 20 times compared with that of 1-dimensional GC-MS reference method. This developed method could be suitable for qualitative and quantitative analyses to determine the contamination level of trace FAME in AVTUR.

• Journal of the Korean Society of Marine Environment & Safety
• /
• v.29 no.6
• /
• pp.704-711
• /
• 2023

This paper discusses the control method of BLDC(Brushless Direct Current) motor that has similar electrical characteristics with DC motor but has improved its lifespan and reliability. The BLDC motor can improve durability and speed stability by using rotor position information to eliminate commutators that require mechanical contact with DC motors. In this study, a controller for a DC motor was designed based on the fact that the current in the windings of a BLDC motor is a square-wave current like the current flowing in the armature of a DC motor. Next, the designed controller was applied to a 3-phase BLDC motor to confirm the effectiveness of the controller. In detail, a single-phase DC motor with electrical parameter values of a three-phase BLDC motor was modeled and a PI controller for motor speed control was designed by applying the root locus method to the derived system. The speed control simulation of the DC motor was performed to confirm the validity of the controller, and the same controller was applied to the speed control of the 3-phase BLDC motor implemented in MATLAB. From the simulation, similar results of the DC motor were obtained in the 3 phase BLDC motor and confirmed the usefulness of the proposed control scheme.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.7 no.6
• /
• pp.63-69
• /
• 2008

Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range ($4.2{\sim}5.4\;GHz$) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is $5.3{\sim}6.0\;mW$ at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is $-180.84{\sim}-180.5$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.65-73
• /
• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Korean Society for Railway
• /
• v.19 no.6
• /
• pp.727-735
• /
• 2016

Smart transformers are effective at reducing the weight and increasing the efficiency of traction systems for railroad applications. A smart transformer generally consists of rectifier modules and the Dual-Active-Bridge (DAB) converter modules. The efficiency of the smart transformer depends on not only the electrical characteristics, but also on the control method of the converter modules. Especially, a DAB converter has a high order degree of freedom of voltage modulation to control the power transferred through the high frequency transformer, and a voltage modulation method, are very critical for the efficiency of the DAB converter. This paper proposes a new voltage modulation method for the DAB converter to increase the efficiency in the low/medium power transfer condition. The proposed modulation method controls the reactive power in the high frequency transformer, making it zero. And, the switching loss is dramatically reduced by using the received converter module as a diode rectifier. The feasibility of the proposed modulation method is verified by computer simulation of the 900Vdc DAB converter power control.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.10
• /
• pp.1031-1041
• /
• 2009

A small microstrip monopole antenna for macro-micro frequency tuning over multiple bands is presented. The meander-shape antenna is fabricated on a conventional printed circuit board(FR-4, $\varepsilon_r=4.4$ and tan $\delta=0.02$). The antenna operates over WiBro(2.3~2.4 GHz) and WLAN a/b(2.4~2.5 GHz/5.15~5.35 GHz) service bands with an essentially constant antenna gain within each service band. Two diodes, a PIN diode and a varactor, are embedded into the antenna for frequency reconfiguration. The PIN diode is used for frequency switching(macro-tuning) between 2 GHz and 5 GHz bands while the varactor is used for frequency tuning(micro-tuning) within the service bands, 2.3~2.5 GHz and 5.15~5.35 GHz. Unwanted resonances between the two frequency bands(2 GHz and 5 GHz) are suppressed by filling up the gaps between the meander lines. The antenna gain is essentially constant and higher than 2 dBi within each service band. The measured performance of the proposed antenna system suggests the macro-micro frequency tuning techniques be useful in reconfigurable wireless communication systems.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.3
• /
• pp.199-205
• /
• 2017

In a small cell base station used in densely populated areas, a dual polarized multiple antenna(MIMO) is mainly used to increase the cell capacity. This paper demonstrates a dual-polarization antenna with high cross-polarization discrimination(XPD) that can improve the capacity of a small cell using a dual polarization multiple antenna (MIMO). By using the symmetric structure and differential feeding, high XPD in all directions is achieved. In addition, a very similar radiation pattern is observed between each polarization. Because of high XPD and similar radiation pattern in all directions, proposed antenna is well adopted for small-cell multiple-input multiple-output(MIMO) system. Experimental results shows that the proposed antenna has a bandwidth of 180 MHz (2.51~2.7 GHz), a maximum gain of 4.5 dBi (3.5~4.5 dBi), and a half-power beam width of 85 degrees. In addition, average XPD of 26.4 dB in all directions, more than 13.8 dB increase than previous dual-polarization antennas which use single emitter by using different feeding or selectively use polarization through switching.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.148-156
• /
• 2013

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through independently operating in each dedicated time periods. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple was 11 mV at 3.3V output voltage. Over/undershoot voltage was 10mV/19.6mV at 3.3V output voltage. The noise performance was simulated at 800mA and 100KHz load regulation. Core circuit can be implemented small size in $700{\mu}m{\times}800{\mu}m$ area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD $0.35{\mu}m$ technology.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.4
• /
• pp.16-24
• /
• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.11
• /
• pp.1034-1046
• /
• 2011

In this paper, a design and fabrication of 40 W power amplifier for the X-band using load-pull measurement of GaN HEMT chip are presented. The adopted active device for power amplifier is GaN HEMT chip of TriQuint company, which is recently released. Pre-matched fixtures are designed in test jig, because the impedance range of load-pull tuner is limited at measuring frequency. Essentially required 2-port S-parameters of the fixtures for extraction optimal input and output impedances is obtained by the presented newly method. The method is verified in comparison of the extracted optimal impedances with data sheet. The impedance matching circuit for power amplifier is designed based on EM co-simulation using the optimal impedances. The fabricated power amplifier with 15${\times}$17.8 $mm^2$ shows the efficiency above 35 %, the power gain of 8.7~8.3 dB and the output power of 46.7~46.3 dBm at 9~9.5 GHz with pulsed-driving width of 10 usec and duty of 10 %.