• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.164-165
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• 2013

멀티프로세서에서 시스템의 병렬성을 향상시키기 위해서 멀티스레드 프로그램을 이용한다. 이러한 멀티스레드 프로그램은 스레드간 역할을 분담하여 작업을 진행하게 된다. 멀티스레드 프로그램에는 생산자-소비자 구조가 있다. 기존 메모리할당자들은 생산자-소비자 구조에 대한 연구가 진행되지 않고, 크리티컬 섹션이 긴 락을 사용하여 성능상에 문제가 있다. 우리는 이러한 문제점을 독특한 메모리 해제 방법을 통해 해결하였고, 실험을 통해 메모리 할당자의 속도가 향상되는 것을 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.1020-1023
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• 2008

멀티스레드 프로그램의 효과적인 디버깅을 위해서는 스레드의 비결정성에 의해 야기되는 다양한 수행 양상의 직관적인 이해가 중요하다. 스레드 수행 양상을 시각화하는 기존의 기법들은 공유 변수의 접근사건들 간의 부분 순서를 표현함으로써 시각적 복잡도가 높거나 이전 수행에서 결정된 락킹 순서를 표현하여 잠재되어 있는 다른 수행 양상에 대한 정보를 제공하지 못 한다. 본 논문은 프로그램 수행의 비결정적인 부분 순서는 락의 종류와 속성을 포함하는 코드 블록으로 시각화하고, 결정적인 부분 순서는 블록들을 연결하는 간선으로 시각화한다. 본 연구의 그래프는 플랫폼에 독립적인 Java Swing으로 구현하고 합성 프로그램을 사용하여 효과성을 실험한다.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.575-582
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• 2000

Because FIFO thread scheduling used in the existing multithreaded models does not consider locality in programs, it may result in the decrease of the performance of execution, caused by the frequent context switching overhead and delay of execution of relatively short frames. Quantum unit scheduling enhances the performance a little, but it still has the problems such as the decrease in the processor utilization and the longer delay due to its heavy dependency on the priority of the quantum units. In this paper, we propose shortest-frame-first(SFF) thread scheduling algorithm. Our algorithm selects and schedules the frame that is expected to take the shortest execution time using thread size and synchronization information analyzed at compile-time. We can estimate the relative execution time of each frame at compile-time. Using SFF thread scheduling algorithm on the multithreaded models, we can expect the faster execution, better utilization of the processor, increased throughput and short waiting time compared to FIFO scheduling.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.655-664
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• 2002

In many data-parallel applications massive parallelism can be easily extracted through data distribution. But it often causes very long communication latency. This paper shows that task parallelism, which is extracted from data-parallel programs, can be exploited to hide such communication latency Unlike the most previous researches over exploitation of task parallelism which has not been considered together with data parallelism, this paper describes exploitation of task parallelism in the context of data parallelism. PCFG(Parallel Control Flow Graph) is proposed to represent a multithreaded program consisting of a few task threads each of which can include a few data-parallel loops. It is also described how a PCFG is constructed from a source data-parallel program through HDG(Hierarchical Dependence Graph) and how the multithreaded program can be constructed from the PCFG.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.99-106
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• 2008

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the reordering of the sequence of program statements. This reordering does not give any problems in a single-threaded program. However, the reordering gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as JavaPathfinder do not consider the reordering resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we develop a new verification tool to verify Java source program based on Java Memory Model. And our tool is capable of handling the reordering in verifying Java programs. As a result, our tool finds an error in the test program which is not revealed with the traditional model checker JavaPathFinder.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.6
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• pp.499-506
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• 2004

The copper foil surface inspection system is necessary for the factory automation and product quality. The developed system is composed of the high speed line scan camera, the image capture board and the processing computer. For the system resource utilization and real-time processing, multi-threaded architecture is introduced. There are one image capture thread, 2 or more defect detection threads, and one defect communication thread. To process the high-speed input image data, the I/O overlap is used through the double buffering. The defect is first detected by the predetermined threshold. To cope with the light irregularity, the compensation process is applied. After defect detection, defect type is classified with the defect width, eigenvalue ratio of the defect covariance matrix and gray level of defect. In experiment, for high-speed input image data, real-time processing is possible with multi -threaded architecture, and the 89.4% of the total 141 defects correctly classified.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.331-339
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• 2017

This paper proposes a thread pool management technique of an websocket server that is applicable to embedded systems. WebSocket is a proposed technique for consisting a dynamic web, and is constructed using HTML5 and jQuery. Various studies have been progressing to construct a dynamic web by Apache, Oracle and etc. Previous web service systems require high-capacity, high-performance hardware specifications and are not suitable for embedded systems. The node.js which is consist of HTML5 and jQuery is a typical websocket server which is made by open sources, and is a java script based web application which is composed of a single thread. The node.js has a limitation on the performance for processing a high velocity data on the embedded system. We make up a multi-thread based websoket server which can solve the mentioned problem. The thread pool is managed by a bit register and suitable for embedded systems. To evaluate the performance of the proposed algorithm, we uses JMeter that is a network test tool.

• Journal of Korea Multimedia Society
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• v.8 no.3
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• pp.355-361
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• 2005

This paper proposed a system collecting image information by agents in multi-threaded environment and then retrieving them with content based image retrieval. This system uses multi threads to retrieve web information effectively, then improves efficiency of CPU cycles to reduce latency time, which is the time requesting queries, executing communication processing 4hat the retrieval agents perform and filtering the retrieval results. Also, the agents for image retrieval use Java language, which is platform independent, to be suitable for distributed environment. Using JDBC to save the retrieved images, the agents are connected to database. The images themselves are stored in distributed agents' databases, and only the image indexes are stored in an index server so that the efficiency of storage and retrieval time can be improved.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.252-255
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• 2010

고해상도의 동영상 서비스가 보편화 되면서 동영상을 빠르게 처리를 위한 연구가 활발히 이루어 지고 있다. 그리고 멀티코어 프로세서의 사용이 증가 하고 멀티코어 시스템에서 H.264/AVC 디코더를 구현하기 위하여 다양한 병렬화 방법이 제안되고 있다. 하지만 H.264/AVC디코더의 병렬화를 진행하는 과정에서 각 스레드에서 처리하는 데이터의 처리시간 차이로 인하여 스레드의 동기를 확인 해야 한다. 이로 인하여 병렬화를 통한 성능 향상의 걸림돌이 된다. 우리는 이러한 병렬화 과정에서 발생하는 문제점을 고려하여 효과적으로 H.264/AVC 디코더를 병렬화 하는 방법에 대하여 연구하였다. 우리가 제안하는 Frame Partition based Parallelization (FPP) 방법은 프레임을 매크로 블록 묶음으로 나누어 병렬화 한다. 그리고 병렬화 과정에서 스레드를 처리하는 방법을 개선하여 성능을 향상 시켰다. 본 논문에서는 FFmpeg H.264/AVC 디코더를 이용하여 실험 하였고 인텔 쿼드 코어 기반의 멀티코어 시스템에서 멀티 스레드로 구현하였다. 우리는 FPP 방법을 적용하여 병렬화 방법 적용 전 H.264/AVC 디코더와 비교하여 최대 53%의 성능 향상을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.512-521
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• 2002

Recently, conventional superscalar RISC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(Instructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.