• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.18-24
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• 2012

High current behaviors of the extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOSFET) for electrostatic discharge (ESD) protection of high voltage operating LDI (LCD Driver IC) chip are analyzed. Both the transmission line pulse (TLP) data and the thermal incorporated 2-dimensional simulation analysis demonstrate a characteristic double snapback phenomenon after triggering of biploar junction transistor (BJT) operation. Also, background doping concentration (BDC) is proven to be a critical factor to affect the high current behavior of the EDNMOS devices. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.

• Journal of Satellite, Information and Communications
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• v.8 no.2
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• pp.36-43
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• 2013

In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

• Transactions of the Korean Society of Mechanical Engineers
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• v.14 no.3
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• pp.503-512
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• 1990

In this study, a penalty method effective for the case that has no snap-back phenomenon, is proposed and an adaptive method which choose the penalty method or Riks' type method, is suggested for the case of snap-back problem. And for the case that loads are applied to one or more points of a structure, the Riks' method is applied in general, but under certain condition choice of new incremental load parameter is suggested to accelerate the convergence rate. Finally, for the case that displacements of a structure are controlled at one or more points Riks' type method is proposed. In this case, the proposed method is applied in general but under certain condition it is recommended to choose other incremental displacement parameter to eliminate probable divergence. Five examples are analysed and compared with the result of published literature.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.21 no.11
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• pp.1931-1942
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• 1997

A new load/displacement parameter method is developed for the cases that loads are applied to one or more points, and displacements of a structure are controlled at one or more points sinultaneously. The procedure exploits a generalized Riks method, which utilizes load/displacement parameters as scaling factors in order to analyze the post-buckling phenomena including snap-through or snap-back. A convergence characteristic is improved by employing new relaxation factors in incremental displacement parameter, particularly at the region where exhibits severe numerical instability. The improved performance is illustrated by means of numerical example.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.12-17
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• 2014

In this paper, modified EDNMOS device with DPS (double polarity source) structure are suggested to realize stable and robust ESD (electrostatic discharge) protection performance of high voltage operating microchip. This DPS structure inserts the P+ diffusion layer on N+ source side, which in intended to block lateral extension of the electron rich region from N+ source side. Based on our simulation results, the inserted P+ diffusion layer effectively prevents the formation of deep electron channeling induced by high electron injection. As a result, our proposed DPS_EDNMOS devices could overcome the double snapback effect of conventional Std_EDNMOS device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.40-50
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• 2010

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.