• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.184-184
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• 2010

Write-once-read-many times (WORM) 메모리 소자는 1회에 한해 쓰기 가능한 저장 장치로서 반영구적인 기록 보존을 필요로 하는 분야에서 널리 사용되는 저항 구조의 비휘발성 메모리 소자이다. 무기물을 사용한 WORM 메모리 소자의 제작과 소자의 전기적 특성에 관한 많은 연구가 활발히 진행되었으나 절연성 고분자인 Polystyrene (PS) 박막에 분산된 ZnO 나노입자를 이용한 무기물/유기물 복합 구조의 WORM 메모리 소자에 관한 연구는 상대적으로 미흡하다. 본 연구에서는 ZnO 나노입자가 분산되어 있는 PS를 스핀코팅 방법으로 박막 형태로 증착하여 WORM 메모리 소자를 제작하고 전기적인 성질을 조사하였다. 소자를 제작하기 위해 ZnO 나노 입자와 PS를 용매인 N,N-디메틸포메미드에 혼합하여 소자를 제작하였다. 그 후 하부 전극인 ITO가 증착되어 있는 유리 기판 위에 ZnO와 PS가 분산되어 있는 고분자 용액을 스핀 코팅 방법으로 도포한 후에 열을 가해 용매를 제거하여 박막을 형성하였다. ZnO 나노입자가 분산되어 있는 PS 박막 위에 Al을 상부 전극으로서 증착하였다. 전압을 인가하여 측정한 전류-전압 특성은 1.5 V에서 소자의 전도도가 크게 향상이 되는 것을 관측하였다. 읽기 전압에서 낮은 전도도(OFF 상태)와 높은 전도도 (ON 상태)의 크기는 $10^3$으로 이며, ON 상태가 된 이후에는 OFF 상태로 전환되지 않는 전형적인 WORM 메모리 소자의 특성이 관측되었다. ZnO 나노 입자가 없이 PS 만으로 박막을 제작한 소자는 쌍안정성 특성이 나타나지 않았다. 따라서 소자에서 전류 쌍안정성으로 나타난 원인은 PS안에 분산되어 있는 ZnO 나노입자에 기인함을 알 수 있었다. 제작된 WORM 메모리 소자의 기억 유지 특성에 대한 결과는 장시간에 걸친 측정에서 ON 전류 및 OFF 전류의 변화가 거의 없었다. 이 실험 결과는 제작된 무기물/유기물 복합 구조를 가진 WORM 메모리 소자는 우수한 기억 특성을 가지고 있으며 반영구적인 메모리 소자로 사용할 수 있음을 제시하고 있다.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.98-113
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• 2009

Conventional file systems for harddisk drive cannot be applied to NAND flash memory, because the physical characteristics of NAND flash memory differs from those of harddisk drive. To address this problem, various file systems with better reliability and efficiency have also been developed recently. However, those file systems have inherent overheads for updating the file's metadata pages, because those file systems save file's meta-data and data separately. Furthermore, those file systems have a critical reliability problem: file systems fail when either a page in meta-data of a file system or a file itself fails. In this paper, we propose a self-description page technique and In Memory Core File System technique to address these efficiency and reliability problems, and develop SDFS(Self-Description File System) newly. SDFS can be safely recovered, although some pages fail, and improves write and read performance by 36% and 15%, respectively, and reduces mounting time by 1/20 compared with YAFFS2.

• Journal of IKEEE
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• v.27 no.3
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• pp.327-332
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• 2023

CNTFET, which is receiving high attention as a next-generation semiconductor candidate due to its higher performance and various utilization than traditional silicon-based semiconductor devices, is having difficulty in commercialization because its unique process deviation such as CNT placement has not yet matured. To overcome this difficulty, numerous studies have been continuously conducted to take advantages of CNTFET and compensate its weakness by implementing circuits, which are less affected by process deviation due to repetitive circuit placement, into MOSFET-CNTFET based hybrid circuits. This paper compares how much the performance of the hybrid SRAM can be changed by semiconductor process variation existing in the traditional MOSFET SRAM or CNTFET SRAM. Simulation results show that, if the CNT density can be maintained between 7 and 9 per 32nm, hybrid SRAM is about 2.6 times and about 1.1 times more robust to process deviation than conventional MOSFET SRAM in read and write operations, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.5
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• pp.74-82
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• 2011

SSD has a limitation of number of erase/write cycles and does not allow in-place update unlike the hard disk because SSD is composed of an array of NAND flash memory. Thus, FTL is used to effectively manage SSD of having different characteristics from traditional disk. FTL has page, block, log-block mapping method. Among then, when log-block mapping method such as BAST and FAST is used, the performance of SSD is degraded because frequent merge operations cause lots of pages to be copied and deleted. This paper proposes a data allocation and replacement method based on access frequency by allocating PRAM as checking area of access frequency, log blocks, storing region of hot data in SSD. The proposed method can enhance the performance and lifetime of SSD by storing cold data to flash memory and storing log blocks and frequently accessed data to PRAM and then reducing merge and erase operations. Besides, a data replacement method is used to increase utilization of PRAM which has limitation of capacity. The experimental results show that the ratio of erase operations of the proposed method is 46%, 38% smaller than those of BAST and FAST and the write performance of the proposed method is 34%, 19% higher than those of BAST and FAST, and the read performance of the proposed method is 5%, 3% higher than those of BAST and FAST, respectively.

• Journal of the Korean BIBLIA Society for library and Information Science
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• v.30 no.1
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• pp.5-27
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• 2019

This study analyzed the effects of comic book reading program on Korean proficiency and acculturation of youth with immigration background, by conducting a six-month reading program with five teenagers with immigration background. Ten comic books were selected from published by School Library Journal, based on the themes - that are related to the lives of youth with immigration background - and interests of participating teens. According to the literacy skills test conducted before and after the reading program, the participating teens' Korean proficiency has generally improved, particularly in the areas of interpretation and vocabulary. In terms of writing, grammatically incorrect sentences, phrases, and expressions have declined. Most participants showed stable adjustment to Korean culture, but one participant who felt still insecure of her ethnic identity deeply empathized with one of the characters of the books, and shared the difficulties of living as an outsider of a society. The participants of this research learned or rediscovered the joy of reading through this comic book reading program; at the end of the program, many of them expanded their interest in reading novels, books without any illustrations.

• Journal of KIISE
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• v.43 no.5
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• pp.524-530
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• 2016

The desire to access data faster and the growth of next-generation memories such as non-volatile memories, contribute to the development of research on memory file systems. It is recommended that memory mapped file I/O, which has less overhead than read-write I/O, is utilized in a high-performance memory file system. Memory mapped file I/O, however, brings a page table overhead, which becomes one of the big overheads that needs to be resolved in the entire file I/O performance. We find that same overheads occur unnecessarily, because a page table of a file is removed whenever a file is opened after being closed. To remove the duplicated overhead, we propose the mapping cache, a technique that does not delete a page table of a file but saves the page table to be reused when the mapping of the file is released. We demonstrate that mapping cache improves the performance of traditional file I/O by 2.8x and web server performance by 12%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.5
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• pp.2092-2099
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• 2013

Through the data transfer race in industry since 1990s, the operational speed of optical disk drive(ODD) becomes commonly over 10,000 rpm. Such high speed operation inevitably causes the vibration, which is also the disturbances in the read-write process of pick-up servo-controller. Generally the vibration disturbance problem can be solved by the vibration isolation using the rubber mount and the increase of robustness of the pick-up servo-controller. Optical disk itself has not been targeted for the vibration reduction, because it is manufactured under the standardized format. In this paper we focused on the increase of critical speed of optical disk, that is, the improvement of dynamic characteristics, with the control of residual stresses which are come from the injection molding process. To do this, first, the residual stresses induced from the injection molding process are calculated using finite element method. The major design parameters of the process conditions are flow rate and melt temperature, which control the residual stresses in optical disk. Second, the critical speed of optical disk is calculated with modal analysis considering residual stress distributions. It was found out that the critical speed can be improved by the control of operational parameters in the injection molding process.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.223-228
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• 2005

Several researchers have pointed out that the energy consumption in memory takes a dominant fraction on the energy budget of a whole embedded system. This applies to the embedded Java virtual machine tn, and to develop a more energy-efficient JVM it is absolutely necessary to optimize the energy usage in Jana memory. In this paper we have analyzed the logical memory access pattern in JVM as it executes numerous number of bytecode instructions while running a Java program. The access pattern gives us an insight how to design and select a suitable memory technology for Java memory. We present the memory access pattern for the three logical data spaces of JVM: heap, operand stack, and local variable array. The result saws that operand stack is accessed most frequently and uniformly, whereas heap used least frequently and non-uniformly among the three. Both heap and local variable array are accessed mostly in read-only fashion, but no remarkable difference is found between read and write operations for operand stack usage.