• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.137-146
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• 2005

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1154-1162
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• 2016

This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.31 no.5
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• pp.227-234
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• 2018

Researches regarding measurement and control of the dynamic behavior of liquid such as sloshing have been actively on undertaken in various engineering fields. Liquid vibration is being measured in the study of tuned liquid dampers(TLDs), which attenuates wind motion of buildings even in building structures. To overcome the limitations of existing wave height measurement sensors, a method of measuring liquid vibration in a TLD using a laser Doppler vibrometer(LDV) and galvanometer scanner is proposed in this paper: the principle of measuring speed and displacement is discussed; a system of multi-point measurement with a single point of LDV according to the operating principles of the galvanometer scanner is established. 4-point liquid vibration on the TLD is measured, and the time domain data of each point is compared with the conventional video sensing data. It was confirmed that the waveform is transformed into the traveling wave and the standing wave. In addition, the data with measurement delay are cross-correlated to perform singular value decomposition. The natural frequencies and mode shapes are compared using theoretical and video sensing results.