• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.6
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• pp.286-295
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• 2006

This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.

• Journal of Satellite, Information and Communications
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• v.7 no.1
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• pp.128-133
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• 2012

In this paper, we analysis the effect of error of code tracking and frequency tracking according to the chip delay of spoofing signal through the simulation. Firstly, we investigate the type of spoofing signal and defense technical of spoofing attack. For simulation, we generated the intermediate spoofing signal using the software GNSS signal generator simulator(SGGS), the intermediate spoofers synchronize its counterfeit GPS signals with the current broadcast GPS signals. The software GPS receiver simulator(SGRS) received the spoofing signal and normal signal from SGGS, and process the signals. In paper, we can check that the DLL and PLL tracking loop error are generated and pseudo-range is changed non-linear according to chip delay of spoofing signal when the spoofing signal is entered. As a result, we can check that navigation solution is incorrectly effected by spoofing signal.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.68-70
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• 1998

본 논문에서는 클록들을 주기적으로 동기화하는 분산 실시간 시스템에서 주어진 태스크의 시간 제약(timing constraint)을 변환시는 구가지 기법을 제안한다. 전형적인 이산 클록 동기화(discrete clock synchronization)알고리즘은 클록의 값을 순간적으로 보정(correct)하여 클록의 시간이 불연속적으로 진행학 한다. 이러한 시간상의 불연속성은 태스크의 시작제한시간(release time)이나 종료시한(deadline)과 같은 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다. 클록 시간의 불연속성을 피하기 위해 일반적으로 연속 클록 동기화(continuous clock synchronization) 기법이제안되었지만 소프트웨어적으로 구현되기에는 많은 오버헤드를 유발시키는 문제점이 있다. 이에 따라 연속 클록 동기화는 PLL (Phase-Locked Loop)을 이용한 별도의 하드웨어를 사용하는 것이 보통이다. 본 논문에서는 연속 클록 동기화 기법을 사용하는 대신, 태스크의 시간 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였다. DCT는 소프트웨어 으로 구현이 가능하여 새로운 하드웨어를 필요로 하지 않으며, 이를 통해 기존의 이산적으로 동기화된 시스템에서 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있다. 또 다른 문제점으로서, 클록의 물리적인 특성으로 인해 동기화된 클록들이 상한된(bounded from the above)오차(skew)를 갖는다는 것이다. 이러한 오차는 지역 클록(local clock)에 대해 만족될 수 있는 임의의 실기간 제약 조건이 전역 클록(global clock)에 대해서는 만족되지 않을 수 있음을 의미한다. 본 논문에서는 이를 위해 먼저 두 가지의 스케줄링 가능성, 지역적 스케줄링 가능서(local schedulability)과 전역적 스케줄링 가능성(global schedulability)을 정의하고, 실시간 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation)기법을 제안하였다. SCT를 통해 지역적으로 스케줄링 가능한 태스크는 전역적으로 스케줄링이 가능하므로, 단지 지역적 스케줄링 가능성만을 검사하면서 스케줄링 문제를 해결할 수 있도록 하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.10 s.89
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• pp.952-960
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• 2004

PSK(Phase Shift Keying) is useful because of the power and spectral efficient modulation. In this paper, no additional hardware will be needed to support various transmit mode in the suggested DSP scheme. We design and implement the synchronization algorithm for M-ary PSK(M=2, 4) demodulator based on DSP scheme, instead of complex analog PSK demodulator. TMS320C6203 is used as DSP. We check the all kinds of waveforms via the graph view window after software programming the emulation on the DSP tool. The result of implementation proves that demodulator using the suggested algorithm has equal performance with demodulator using analog circuits.

• Journal of Institute of Control, Robotics and Systems
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• v.16 no.2
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• pp.188-193
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• 2010

With GPS being the primary navigation system, Loran use is in steep decline. However, according to the final report of vulnerability assessment of the transportation infrastructure relying on the global positioning system prepared by the John A. Volpe National Transportation Systems Center, there are current attempts to enhance and re-popularize Loran as a GPS backup system through the characteristic of the ground based low frequency navigation system. To advance the Loran system such as Loran-C modernization and eLoran development, research is definitely needed in the field of Loran-C receiver signal processing as well as Loran-C signal design and the technology of a receiver. We have developed a set of Matlab tools, which implement a software Loran-C receiver that performs the receiver's position determination through the following procedure. The procedure consists of receiving the Loran-C signal, cycle selection, calculation of the TDOA and range, and receiver's position determination through the Least Square Method. We experiences the effect of an incorrect cycle selection and various error factors (ECD, ASF, sky wave, CRI, etc.) from the result of the Loran-C signal processing. It is apparent that researches which focus on the elimination and mitigation of various error factors need to be investigated on a software Loran-C receiver. These aspects will be explored in further work through the method such as PLL and Kalman filtering.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.502-511
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• 2012

As the importance of GNSS system increases, the necessity of independent system is increased also. When the independent GNSS system is required, GNSS signal design is necessary with requirement definition. This paper suggests the design method of GNSS signal using the analysis result of receiver performance. First, the candidates are defined based on the design elements. Then the receiver performance of the candidates is analyzed based on the performance evaluation parameters. The weights of performance evaluation parameter are defined in order to consider the receiver performance in a various aspects. Finally, the calculation of normalized performance evaluation parameters and weights are derived to obtain the compared value for signal selection. Spreading code, modulation method and carrier frequency are considered as design parameters. Also, correlation width, DLL PLL thermal noise jitter, frequency bandwidth and side lobe peak ratio are considered as performance evaluation parameters. And positioning performance, robustness to noise, bandwidth efficiency are considered as the performance aspects. This paper analyzes the performance of each candidate using software based simulator and suggest the method to compare objectively the performance of each candidates.