• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2120-2130
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• 1998

This paper concerns a design of programmable MPEG decoder for video processing by object unit on network. The decoder can process video data effectively by a embedded controller with stack buffers for supporting OOP (Object-Oriented Programming). The controller offers extended instructions that process several data types including 32bit integer type. In addition to that, we have a vector processor, in this decoder that can execute advanced compensation and prediction by half pixel and SA(Shape Adaptive)-IDCT of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We verified the decoder with $0.6\mu\textrm{m}$ 5-Volt CMOS COMPASS library.

• Convergence Security Journal
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• v.18 no.5_1
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• pp.19-24
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• 2018

For a long time now, general-purpose processors have provided dedicated hardware / software tracing modules to provide developers with tools to fix bugs. A hardware tracer generates its enormous data into a log that is used for both performance analysis and debugging. Processor Trace (PT) is a new hardware-based tracing feature for Intel CPUs that traces branches executing on the CPU, which allows the reconstruction of the control flow of all executed code with minimal labor. Hardware tracer has been integrated into the operating system, which allows tight integration with its profiling and debugging mechanisms. However, in the Windows environment, existing studies related to PT focused on decoding only one flow in sequence. In this paper, we propose an extended PT decoder structure that provides basic data for real-time trace and malicious code detection using the functions provided by PT in Windows environment.

• Proceedings of the Korean Society of Computer Information Conference
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• 2022.07a
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• pp.137-138
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• 2022

소스 코드 식별자의 이름을 잘 정하는 것은 소프트웨어 엔지니어링에서 중요한 문제로 다루어지고 있다. 프로그램 엔티티의 의미있고 간결한 이름은 코드 이해도에 중요한 역할을 하며, 소프트웨어 유지보수 관리 비용을 줄이는 데에 큰 효과가 있다. 이러한 코드 식별자 중 평균적으로 가장 복잡한 식별자는 '메소드 이름'으로 알려져 있다. 본 논문에서는 메소드 내용과 일관성 있는 적절한 메소드 이름 생성을 자연어 처리 태스크 중 하나인 '추상적 텍스트 요약'으로 치환하여 수행하는 트랜스포머 기반의 인코더-디코더 모델을 제안한다. 제안하는 모델은 Github 오픈소스를 크롤링한 Java 데이터셋에서 기존 최신 메소드 이름 생성 모델보다 약 50% 이상의 성능향상을 보였다. 이를 통해 적절한 메소드 작명에 필요한 비용 절감 달성 및 다양한 소스 코드 관련 태스크를 언어 모델의 성능을 활용하여 해결하는 데 도움이 될 것으로 기대된다.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Convergence Security Journal
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• v.18 no.5_1
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• pp.67-73
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• 2018

From a software engineering point of view, tracing is a special form of logging that records program execution information. Tracers using dedicated hardware are often used because of the characteristics of tracers that need to generate and decode huge amounts of data in real time. Intel(R) PT uses proprietary hardware to record all information about software execution on each hardware thread. When the software execution is completed, the PT can process the trace data of the software and reconstruct the correct program flow. The hardware trace program can be integrated into the operating system, but in the case of the window system, the integration is not tight due to problems such as the kernel opening. Also, it is possible to trace only a single process and not provide a way to trace multiple process streams. In this paper, we propose a method to extend existing PT trace program to support multi - process stream traceability in Windows environment in order to overcome these disadvantages.

• Journal of the Korea Society of Computer and Information
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• v.16 no.11
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• pp.1-8
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• 2011

The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.

• KIPS Transactions on Software and Data Engineering
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• v.10 no.12
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• pp.579-586
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• 2021

Time series forecasting refers to predicting future time information based on past time information. Accurately predicting future information is crucial because it is used for establishing strategies or making policy decisions in various fields. Recently, a transformer model has been mainly studied for a time series prediction model. However, the existing transformer model has a limitation in that it has an auto-regressive structure in which the output result is input again when the prediction sequence is output. This limitation causes a problem in that accuracy is lowered when predicting a distant time point. This paper proposes a sequential decoding model focusing on the style transformation technique to handle these problems and make more precise time series forecasting. The proposed model has a structure in which the contents of past data are extracted from the transformer-encoder and reflected in the style-based decoder to generate the predictive sequence. Unlike the decoder structure of the conventional auto-regressive transformer, this structure has the advantage of being able to more accurately predict information from a distant view because the prediction sequence is output all at once. As a result of conducting a prediction experiment with various time series datasets with different data characteristics, it was shown that the model presented in this paper has better prediction accuracy than other existing time series prediction models.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1681-1688
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• 2017

In this paper, we implemented a high-speed signal processing hardware system for Color Line Scan Camera using FPGA and Nor-Flash. The existing hardware system mainly processed by high-speed DSP based on software and it was a method of detecting defects mainly by RGB individual logic, however we suggested defect detection hardware using RGB-HSL hardware converter, FIFO, HSL Full-Color Defect Decoder and Image Frame Buffer. The defect detection hardware is composed of hardware look-up table in converting RGB to HSL and 4K HSL Full-Color Defect Decoder with high resolution. In addition, we included an image frame for comprehensive image processing based on two dimensional image by line data accumulation instead of local image processing based on line data. As a result, we can apply the implemented system to the grain sorting machine for the sorting of peanuts effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.38-48
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• 2007

The increasing demand on the use of multimedia video contents drives more mobile embedded systems to incorporate H.264/AVC decoding capability. An H.264/AVC decoder often requires high computation bandwidth during its decoding phase. Depending upon processor computation capability and multimedia contents complexity, the decoder can be implemented either in hardware or software. However, without a thorough analysis on the Performance and resource requirements, it is difficult to choose a cost-effective methodology of implementing this codec. This paper presents both hardware and software implementation of H.264/AVC decoding subsystem in mobile embedded systems, and quantitatively analyses the performance and resource requirements. It also shows the methodology to identify performance bottleneck in Linux-based mobile embedded systems, which is in turn used to select feasible and efficient implementation methodology.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.481-484
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• 2001

본 논문에서는 MPEG-2 AAC 디코더의 DSP구현에 관한 연구결과로서 IS0/1EC 13818-7 표준에 의거 구현된 MPEC-2 AAC 디코더의 각 세부 기능블럭들의 구성 및 동작원리에 대하여 요약 기술하고. DSP연산에 최적화된 연산구조의 연구를 바탕으로 16bit 고정소수점 연산구조를 가지는 DSP상에서 구현된 MPEG-2 AAC 디로더의 시스템의 하드웨어 및 소프트웨어 구성에 관하여 간략한 기술하였다. 구성된 디코더의 성능평가를 통하여 MPEC-2 AAC 비트스트림을 디코딩하기 위하여 필요로 하는 연산량 및 소요 메모리의 양을 측정하고, 디코더 성능의 중요 척도인 음질평가를 수행하였다. 수행방법으로서 conformance test에 의거하여 PSNR을 측정함으로써 객관적인 성능 지표의 제시와 함께, 주관적인 음질 평가도 병행하여 수행하였다.