• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.397-400
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• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.116-123
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• 2013

In mobile healthcare applications, the reliable transmission of the bio-data is very important. In this article, we present a reliable bio-data transmission technique for mobile healthcare monitoring service at 6LoWPAN multi-hop wireless networks. In particular, we expand IEEE 11073-20601 protocol, and propose the reliable path construction for 6LoWPAN aimed to reliably provide mobile healthcare service over wireless sensor network, using IPv6 network. 6LoWPAN is recognized possibility because it is agree with sensor network by raising Adaptation layer on the MAC layer to transmit IPv6 packets. In this article proposed minimize the algorithm complexity and reliability routing protocol because the 6LoWPAN devices are suitable for low cost, small size and battery that can be used to health care system environment. And detailed procedures and algorithms are presented. We the proposed method to prove the superiority of using NS-3 for compareing with AODV protocol.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.12
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• pp.1222-1228
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• 2008

A small satellite, DubaiSat-1 FM(Flight Model), which is based on SI-200 standard bus platform and scheduled to be launched in 2008, is being developed by Satrec Initiative and EIAST(Emirates Institution for Advanced Science and Technology). The TCS(Thermal Control Subsystem) of DubaiSat-1 FM has been designed to mainly utilize passive thermal control in order to minimize power consumption, but the active control method using heaters has been applied to some critical parts. Also, thermal analysis has been performed for DubaiSat-1's mission orbit using a thermal analysis model. The thermal design is modified and optimized to satisfy the design temperature requirements for all parts according to the analysis result. The thermal control performance of DubaiSat-1 FM is verified by thermal vacuum space simulation, consisting of thermal cycling and thermal balance test. Also, to validate the thermal modeling of DubaiSat-1 FM, comparison of test results with analysis has been performed and model calibration has been completed.

• The KIPS Transactions:PartC
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• v.16C no.4
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• pp.495-504
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• 2009

Wireless sensor networks (WSN) consisting of a largenumber of sensors aims to gather data in a variety of environments and is beingused and applied in many different fields. The sensor nodes composing a sensornetwork operate on battery of limited power and as a result, high energyefficiency and long network lifetime are major goals of research in the WSN. Inthis paper we propose a novel cluster-based local multi-hop routing protocolthat enhances the overall energy efficiency and guarantees reliability in thesystem. The proposed protocol minimizes energy consumption for datatransmission among sensor nodes by forming a multi-hop in the cluster.Moreover, through local cluster head rotation scheme, it efficiently manageswaste of energy caused by frequent formation of clusters which was an issue inthe existing methods. Simulation results show that our scheme enhances energyefficiency and ensure longer network time in the sensor network as comparedwith existing schemes such as LEACH, LEACH-C and PEACH.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.61-66
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• 2005

This paper describes a 10-bit 210MHz CMOS current-mode Digital-to-Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a $0.35{\mu}m$ CMOS double-poly four-metal technology rate of 210MHz, DNL/INL of ${\pm}0.7LSB/{\pm}1.1LSB$, a glitch energy of $76pV{\cdot}sec$, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and power dissipation of 83mW at 3.3V

• Journal of Internet Computing and Services
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• v.14 no.5
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• pp.39-48
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• 2013

A cloud system has to deal with highly variable workloads resulting from dynamic usage patterns in order to keep the QoS within the predefined SLA. Aside from the aspects regarding services, another emerging concern is to keep the energy consumption at a minimum. This requires the cloud providers to consider energy and performance trade-off when allocating virtualized resources in cloud data centers. In this paper, we propose a resource provisioning approach based on dynamic thresholds to detect the workload level of the host machines. The VM selection policy uses utilization data to choose a VM for migration, while the VM allocation policy designates VMs to a host based on its service reputation. We evaluated our work through simulations and results show that our work outperforms non-power aware methods that don't support migration as well as those based on static thresholds and random selection policy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.183-190
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• 2004

This paper proposes a methodology to solve problems upon the circuit design applied to inductor load by applying a circuit to improve power factor with is partial switching PFC module to the power supply system for cooling/heating inverter air conditioner and by designing an input power section in compliance with IEC555-2 on the basis of better input power factor and minimized harmonic components of current. On the other hand, this paper suggested how to control the increase of output voltage along with tぉw current waves and partial switching PFC circuit as well, which can provide the output as twice as input voltage This study applied a method to control the compressors of air conditioner by means of increased the voltage applicable to compressor motor by lowering switching number conclusively, it could solve questions about efficiency, economics, electronic noise and so forth. and so that the reasonable voltage for running moor could be set up along with lower power consumption of air conditioner than estimated It was demonstrated that total sum of energy efficiency to operate system was increased to the extent of valid level. And all this merits and appropriateness was proved by computer simulation and experience.

• KNOM Review
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• v.24 no.1
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• pp.1-12
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• 2021

VM (Virtual Machine) live migration is a server virtualization technique for deploying a running VM to another server node while minimizing downtime of a service the VM provides. Currently, in cloud data centers, VM live migration is widely used to apply load balancing on CPU workload and network traffic, to reduce electricity consumption by consolidating active VMs into specific location groups of servers, and to provide uninterrupted service during the maintenance of hardware and software update on servers. It is critical to use VMlive migration as a prevention or mitigation measure for possible failure when its indications are detected or predicted. In this paper, we propose two VNF live migration methods; one for predictive load balancing and the other for a proactive measure in failure. Both need machine learning models that learn periodic monitoring data of resource usage and logs from servers and VMs/VNFs. We apply the second method to a vEPC (Virtual Evolved Pakcet Core) failure scenario to provide a detailed case study.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.10
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• pp.895-903
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• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.