• Journal of KIISE:Computing Practices and Letters
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• v.15 no.9
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• pp.617-625
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• 2009

NAND flash memory is widely used in embedded systems because of many attractive features, such as small size, light weight, low power consumption and fast access speed. However, it requires garbage collection, which includes erase operations. Erase operation is very slow. Besides, the number of the erase operations allowed to be carried out for each block is limited. The proposed garbage collection method focuses on minimizing the total number of erase operations, the deviation value of each block and the garbage collection time. NAND flash memory consists of pages of three types, such as valid pages, invalid pages and free pages. In order to achieve above goals, we use a page rate to decide when to do garbage collection and to select the target victim block. Additionally, We implement allocating method and group management method. Simulation results show that the proposed policy performs better than Greedy or CAT with the maximum rate at 82% of reduction in the deviation value of erase operation and 75% reduction in garbage collection time.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.10
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• pp.1298-1304
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• 2019

Since the 9·11 terror attack in 2001, the Maritime Logistics Security System has been strengthened and required X-ray image for every imported cargos from manufacturing countries to United States. For scanning cargos, the container inspection systems use high energy X-rays for examination of contents of a container to check the nuclear, explosive, dangerous and illegal materials. Nowadays, the X-ray cargo scanners are established and used by global technologies for inspection of suspected cargos in the customs agency but these technologies have not been localized and developed sufficiently. In this paper, we propose the X-ray array detector system which is a core component of the container scanning system. For implementation of X-ray array detector, the analog and digital signal processing units are fabricated with integrated hardware, FPGA logics and GUI software for real-time X-ray images. The implemented system is superior in terms of resolution and power consumption compared to the existing products currently used in ports.

• Journal of the Korean Society for Geothermal and Hydrothermal Energy
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• v.19 no.4
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• pp.8-17
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• 2023

The air temperature is gradually increasing owing to global warming, especially in summer, therefore, the performance of an air source heat pump (ASHP) is expected to be decreased. Accordingly, the performance gap between the ASHP and ground source heat pump (GSHP) should be increased, however, the quantitative comparison has not been yet investigated. In this study, impact of global warming on the performance of the ASHP and GSHP is investigated based on the climate data for 1930, 1980, and 2030. The coefficient of performance (COP) as well as annual power consumption of the ASHP and GSHP are compared and analyzed. In the case of COP, the COP of GSHP hardly changes over the years owing to the constant ground temperature, while that of ASHP decreases by 3.7% for cooling and increases by 0.71% for heating. In the case of annual power consumption, the cooling and heating power consumption of GSHP increases by 12.69% and decreases by 15.58%, respectively, over the year owing to the changes in heating and cooling loads. As for the ASHP, the cooling and heating power consumption increases by 16.64% and decreases by 17.8%, respectively. For a more accurate comparison, power consumption ratio is introduced and shows that total annual power consumption of the GSHP to ASHP decreased from 68% in 1930 to 65% in 2030. Therefore, as global warming accelerates, the effect of reducing power consumption by using GSHP compared to ASHP is expected to be increasing.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.6 s.324
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• pp.59-68
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• 2004

Thanks to the development of microelectromechanical systems(MEMS), wireless communication technology and microsensor technology, it was Possible to manufacture a very small and low costdata acquisition node with sensing function, processing function, wireless communication function and battery. Thus sensor networks begin to be prevailed. The sensor network is a spontaneous system which sets up automatically routing paths and transmits asignificant data to the destination. Sensor nodes requires low-power operation because most of them use a battery as operating power. Sensor nodes transmit a sensing data to the destination. Moreover, they play a router. In fact, because the later consumes more energy than the former, the low-power routing is very important. Sensor networks don't have a routing standard unlike general wireless Ad-hoc networks. So This paper proposes a low-power routing method for anting to sensor networks. It is based on AODV and adapts a method to drop probably RREQ depending on remaining power. We examined it through simulations. From simulation results, we could confirm to reduce power consumption about $10-20\%$ and distribute equally power consumption among nodes.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.1-12
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• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

• Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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• 2010.09a
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• pp.372-375
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• 2010

보안등은 주택가 골목에 안전을 위해 설치하는 중요한 설비로서, 도로 폭이 12m 이하인 장소에 설치된다. 그러내 통행 인구가 없어도 야간시간 내내 점등되고 있기에 낭비되는 전력량이 상당하다. 적외선센서가 부착된 보안등을 교체하게 되면 보행자의 움직임을 통해 일정시간 점등이 되고 이동체가 없을 때는 소등이 되어 전기에너지의 소비를 상당히 줄일 수가 있어 온실가스저감에 기여할 수 있다. 본 논문에서는 적외선센서 보안등의 최적 작동시간을 추적하기 위해 보행자의 통행 분포를 알아보고자 연구지역인 경북대 캠퍼스 내에서 사계절 중 여름철 야간 보행자의 통행패턴을 현장조사하여 분석하였다. 이를 통해 시간별, 공간별 분포 특성을 파악하고 도식화하여 보행자의 통행분포 특성을 파악함으로써 보안등의 작동시간 추적이 가능하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.180-180
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• 2003

FRAM (Ferroelectric Random Access Memory)은 DRAM(Dynamic Random Access Memory)in 커패시터 재료을 상유전체 물질에서 강유전체 물질로 대체하여 전원 공급이 차단되어도 정보를 기억할 수 있고, 데이터의 고속처리가 가능하고 저소비전력과 집적화가 뛰어난 차세대 메모리 소자이다. 본 연구에서는 n-Well/P-Si(100) 기판위에 $Y_2$O$_3$ 박막을 중간층 (buffer layer)으로 사용하여 (Bi,La) Ti$_3$O$_{12}$ (BLT) 강유전체 박막을 졸-겔 방법으로 형성하여 MFM(I)S(Metal Ferroelectric Metal (Insulation) Silicon) 구조의 커패시터 및 전계효과형 트랜지스터(Field Effect Transistor) 소자를 제작하였다. 제작된 소자에 대해 형상학적, 전기적 특성을 조사, 분석하였다.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.8
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• pp.239-244
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• 2015

WebCL was proposed for high complex computing in Javascript. Since WebCL-based applications are distributed and executed on an unspecified number of general clients, it is important to profile their performances on different clients. Several profilers have been introduced to support various programming languages but WebCL profiler has not been developed yet. In this paper, we present a WebCL profiler to evaluate WebCL-based applications and monitor the status of GPU on which they run. This profiler helps developers know the execution time of applications, memory read/write time, GPU statues such as its power consumption, temperature, and clock speed.