• Journal of the Korea Society of Computer and Information
• /
• v.19 no.4
• /
• pp.25-33
• /
• 2014

This paper proposes a power-efficient scheduling scheme that stochastically minimizes the power consumption of real-time tasks while meeting their deadlines on multicore processors. In the proposed scheme, uncertain computation amounts of given tasks are translated into probabilistic computation amounts based on their past completion amounts, and the mean power consumption of the translated probabilistic computation amounts is minimized with a finite set of discrete clock frequencies. Also, when system load is low, the proposed scheme activates a part of all available cores with unused cores powered off, considering the leakage power consumption of cores. Evaluation shows that the scheme saves up to 69% power consumption of the previous method.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06a
• /
• pp.173-175
• /
• 2012

데이터 센터와 같은 대량의 서버를 사용하는 시설이 늘어남에 따라 전력 소모 관리와 열 발생 관리는 매우 중요한 문제가 되었다. 열 관리 연구들의 경우 대부분 열관리의 목적이 시스템의 오류를 방지하는 것이다. 하지만 열 관리에는 많은 전력 소모량이 사용된다. 따라서 열관리를 잘 해주는 것은 전력 관리를 효율적으로 해주는 것이라고 할 수도 있다. 본 논문은 열 관리를 전력 관리라는 측면에서 접근했다. 즉 열 관리에 사용되는 전력과 열로 인해 발생하는 전력을 고려해서 이를 최소화하는 냉각 제어 기법을 구현하였다. 우리가 개발한 냉각 제어 기법을 실제로 실험해서 기존의 냉각 기법과 비교해본 결과 전력 소모량을 17% 감소시키는 것을 확인 할 수 있었다.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.2 no.3
• /
• pp.163-167
• /
• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2016.10a
• /
• pp.158-161
• /
• 2016

모바일 기기의 발전과 함께 다양한 어플리케이션의 기능이 제공되면서 전력에 대해 효율적인 관리가 필요해졌다. 효율적인 관리를 위하여 모바일 디바이스에서의 전력 소모 원인을 분석해야만 한다. 그러나 기존 연구에서 사용되었던 안드로이드 프레임워크의 수정을 통한 전력 분석 방법은 개발에 대한 용이성이 낮은 단점이 존재하고, 프로파일링을 통한 전력 분석 방법은 각 디바이스 모델에 의존적인 단점이 존재한다. 따라서 본 논문에서는 기존 연구들의 문제점을 개선하기 위해서 안드로이드 프레임워크를 수정하지 않고 획득할 수 있는 프로세스와 서비스의 목록 정보를 통해 어플리케이션이 소모하는 전력에 대한 분석을 제안한다. 본 논문에서 제안하는 방법을 GPS를 사용하는 어플리케이션을 분석하기 위해서 적용해보았다. 이를 통해 사용자는 측정된 전력과 함께 해당 전력을 사용하고 있는 프로세스 및 서비스 목록을 확인 할 수 있다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2006.06a
• /
• pp.169-171
• /
• 2006

센서네트워크의 전력소모를 최소화, 최적화하기 위해서는 센서노드들을 실제 환경에 설치하기 이전에 시뮬레이터를 이용하여 센서네트워크의 전력상황을 정확히 추정해야 한다. 이러한 시뮬레이터를 위해서는 센서노드의 소모에너지를 정확히 분석할 수 있는 전력모델이 반드시 요구된다. 본 논문은 센서노드의 소비전력을 정확하게 측정할 수 있는 환경과 방법을 제시하며, 이 환경과 방법을 이용하여 센서노드의 소모전력을 명령어기반과 동작상태기반으로 정확히 측정 분석하고, 센서네트워크 시뮬레이터에 적용할 수 있는 전력모델 개발과정에 대해 소개한다. 전력모델링에 사용된 센서노드는 ATmega128L과 CC2420으로 구성된 Nano-24노드이다.

• Journal of Digital Contents Society
• /
• v.13 no.1
• /
• pp.37-41
• /
• 2012

In this paper, we proposed FPGA algorithm for consider the power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within FPGA. Separated the feasible cluster reduced power consumption using glitch removal method. Glitch removal appled delay buffer insertion method by signal process within the feasible cluster. Also, removal glitch between the feasible clusters by signal process for circuit. The experiments results show reduction in the power consumption by 7.14% comparing with that of [9].

• Journal of Broadcast Engineering
• /
• v.10 no.2
• /
• pp.174-181
• /
• 2005

In this paper, we proposed new fast scattered pilot synchronization techniques to reduce the burst synchronization time for the DVB-H receiving system with robustness. DVB-H terminals employ a TDM system called 'Time-Slicing' to reduce power consumption. In order to fully exploit the potential power reduction, the synchronization time for the DVB-H receiver must be very short. A typical DVB-T system uses the TPS Synchronization to determine the position of scattered pilots which are used for channel estimation, and it takes 68 OFDM symbol time. In this paper, several new fast scattered pilot synchronization techniques are proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.11
• /
• pp.56-62
• /
• 2008

Modern microprocessors must deliver high application performance, while the design process should not subordinate power. In terms of performance and power tradeoff, the instructions window is particularly important. This is because a large instruction window leads to achieve high performance. However, naive scaling conventional instruction window can severely affect the complexity and power consumption. This paper explores an architecture level approach to reduce power dissipation. We propose a low power issue logic with an efficient tag translation. The direct lookup table (DTL) issue logic eliminates the associative wake-up of conventional instruction window. The tag translation scheme deals with data dependencies and resource conflicts by using bit-vector based structure. Experimental results show that, for SPEC2000 benchmarks, the proposed design reduces power consumption by 24.45% on average over conventional approach.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.1
• /
• pp.76-83
• /
• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.2B
• /
• pp.151-161
• /
• 2009

The PULSE protocol can greatly reduce power consumption using a node's sleep state. But this protocol does not consider movement of a sink node in a sensor network. In the mobile sensor network a routing protocol must recover path error by movement of a sink node as quickly as possible. Therefore we have to achieve fast path recovery and power saving to support movement of a sink node in a sensor network. This paper proposes the Mobile PULSE protocol which is a improved routing protocol for a mobile sink node. And we evaluate Mobile PULSE and show that the Mobile PULSE reduces the recovery time about 40% compared with original PULSE protocol. Mobile PULSE increases energy consumption than PULSE as a maximum of 0.8%, which means Mobile PULSE is similar to PULSE in energy consumption. This paper shows mobile PULSE's capability in the mobile sensor network through evaluation of path recovery time and power consumption.