• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.90-95
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• 2014

This paper presents a VHF/UHF-band variable gain low noise amplifier for multi-standard mobile TV tuners. A proposed VHF-band variable gain amplifier is composed of a resistive shunt-feedback low noise amplifier to remove external matching components, a single-to-differential amplifier with input PMOS transcoductors to improve low frequency noise performance, a variable shunt-feedback resistor and an attenuator to control variable gain range. A proposed UHF-band variable gain amplifier consists of a narrowband low noise amplifier with capacitive tuning to improve noise performance and interference rejection performance, a single-to-differential with gm gain control and an attenuator to adjust gain control range. The proposed VHF-band and UHF-band variable gain amplifier were designed in a $0.18{\mu}m$ RF CMOS technology and draws 22 mA and 17 mA from a 1.8 V supply voltage, respectively. The designed VHF-band and UHF-band variable gain amplifier show a voltage gain of 27 dB and 27 dB, a noise figure of 1.6-1.7 dB and 1.3-1.7 dB, OIP3 of 13.5 dBm and 16 dBm, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1125-1134
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• 2011

In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.119-119
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• 2009

인버터 DC 저항용접의 적용성 증대 : 인버터 DC 저항용접 공법이 SPOT, PROJECTON, SEAM, BUTT 등의 공정에 다양하게 적용되어 저항용접 현장에서 고효율, 친환경적 용접 환경을 만드는데 일조 하고 있다. 특히 자동차의 경량화, 충돌내성 증대, 진동 및 내구성 증대, 공간활용 극대화, 새로운 Design 개념 적용 등의 산업전반에 걸쳐 나타나는 신 Trends로 고 장력 철재의 적용 범위가 확대되고 HSS(High Strength Steel), EHSS(Extra High Strength Steel), UHSS (Ultra High strength Steel ; Hot - Formed Steel )등 다양한 철판의 SPOT 저항용접이 필요하게 되었다. 기존의 AC 단상용접의 전력 특성 상 통전 중 무 통전 시간 과 높은 PEAK 전력, 단상 대 전력 소모로 인한 전력 DROP 등의 문제로 인하여 신소재의 용접 시 매우 많은 Spatter가 발생하고, 높은 용접품질의 확보가 어려워 지므로 이를 대체하기 위한 공법으로 MFDC ( 인버터 DC 저항용접공법 )이 적용되고 있다. 인버터 DC 저항용접의 적응제어 : MFDC라는 높은 효율의 용접 전력원이 확보 됨에도 불구하고 용접현장에서는 원 자재, 도금 등의 품질 산포, 프레스 물의 가공산포, 공기압 산포, 전극 과열 및 마모 등의 요인에 의하여 저항용접 산포가 발생하고 있다. 이는 인위적인 조작이 어렵고 불규칙적이며, 어디서나 산재하고 있는 문제이다. 이를 용접전력 제어 법으로 개선하여 일정한 용접성을 확보하기 위한 노력이 적응제어 기법이다. 정 전류, 정 전력 제어는 정량 제어로 용접 물을 비롯한 용접부의 변화와는 관계없이 설정된 일정량의 전력을 공급하기만 하는데 반하여 적응제어는 적절한 용접 작업 시의 용접 물의 상태, 전극의 가압, 표면 상태 등에 따른 변화 페턴을 기억하고 이후 진행되는 용접에 대하여 정상 페턴과의 차이를 감지 이를 보상하므로 고품질의 용접성을 보장하는 제어기법이다. 따라서 다양한 용접 산포 유발 요인에 의해 용접부의 변화가 발생한다 하여도 그 변화를 감지 하고 적절한 용접전력을 공급한다면 고품질의 용접성을 확보하는데 유용한 공법이 될 수 있다. 인버터 DC 저항용접의 SPC 관리 : SPOT 용접 시 획득할 수 있는 다양한 파라메터에 대하여 모니터링 하고 이 자료를 data 화 하여 품질 관리에 응용하게 되면 양산라인에서 반복적으로 발생되는 문제점을 확인 할 수 있고 이를 통계적 방법으로 추적 개선해 나간다면 용접 불량 감소 및 생산성 향상에 도움이 되며 작업자의 공정 능력 향상 및 기업의 기술축적에도 높은 기여를 할 수 있을 것이다. 용접 적응제어와 다양한 파라메터 모니터링이 한 system에서 이루어 질 때 높은 용접성 확보와 불량률 감소, 원가절감, 생산성 향상 등의 효과가 극대화 될 것이다.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• Journal of IKEEE
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• v.26 no.4
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• pp.633-638
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• 2022

Rencently, neuromorphic systems of spiking neural networks (SNNs) that imitate the human brain have attracted attention. Neuromorphic technology has the advantage of high speed and low power consumption in cognitive applications and processing. Resistive random-access memory (RRAM) for SNNs are the most efficient structure for parallel calculation and perform the gradual switching operation of spike-timing-dependent plasticity (STDP). RRAM as synaptic device operation has low-power processing and expresses various memory states. However, the integration of RRAM device causes high switching voltage and current, resulting in high power consumption. To reduce the operation voltage of the RRAM, it is important to develop new materials of the switching layer and metal electrode. This study suggested a optimized new structure that is the Metal/Al₂O₃/HfO_x/SWCNTs/N+silicon (MOCS) with single-walled carbon nanotubes (SWCNTs), which have excellent electrical and mechanical properties in order to lower the switching voltage. Therefore, we show an improvement in the gradual switching behavior and low-power I/V curve of SWCNTs-based memristors.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.5
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• pp.787-799
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• 2023

As IoT devices are widely used at home, IoT automation system that is integrate IoT devices for users' demand are gaining populrity. There is automation rule in IoT automation system that is collecting event and command action. But attacker delay the packet and make time that real state is inconsistent with state recongnized by the system. During the time, the system does not work correctly by predefined automation rule. There is proposed some detection method for delay attack, they have limitations for application to IoT systems that are sensitive to traffic volume and battery consumption. This paper proposes a practical packet delay attack detection technique that can be applied to IoT systems. The proposal scheme in this paper can recognize that, for example, when a sensor transmits an message, an broadcast packet notifying the transmission of a message is sent to the Server recognized that event has occurred. For evaluation purposes, an IoT system implemented using Raspberry Pi was configured, and it was demonstrated that the system can detect packet delay attacks within an average of 2.2 sec. The experimental results showed a power consumption Overhead of an average of 2.5 mA per second and a traffic Overhead of 15%. We demonstrate that our method can detect delay attack efficiently compared to preciously proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.