• Journal of IKEEE
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• v.11 no.2
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• pp.83-88
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• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.987-990
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• 2003

산업현장에서의 인터넷환경 및 원격 제어를 위한 시스템 개발에서 신뢰성이 있고 경제적이며 지능적인 Power Supply가 요구되고 있다. 최근 통신시스템의 Power Supply는 수 kA이상의 출력전류를 가지고 있으며 최소 10개 이상의 모듈로 이루어져 있다. High-End 서버 시스템과 같이 수백 개의 마이크로프로세서를 내장한 시스템은 수십 kW의 전력을 소모한다. 이들이 사용하는 Power Supply는 별도의 시스템 제어기와의 통신으로 시스템에서 발생하는 발열, 소모전력, Total Harmonic Distortion (THD)에 대한 정보를 바탕으로 시스템이 갖는 각각의 Module에 대해 효과적이고 신뢰성 있는 전력공급을 하여야 만다. Distributed Power System (DPS)에서 가장 중요만 역할을 담당하는 Power Factor Correction (PFC) AC-DC Converter의 디지털 제어는 시스템 제어기와의 통신능력을 충분히 고려하면서 DPS를 위한 적합한 솔루션을 제공할 것이다. 본 논문에서는 Digital Signal Processor (DSP)를 사용하여 PFC 제어에 필요한 전파정류전압, 입력전류, 출력전압을 계측하여 역률개선과 THD의 저감을 위한 전류의 추종을 제어하면서 이들 제어기에서의 파라미터를 PC를 통해 모니터하여 최근의 추세를 만족시킬 수 있는 시스템을 구현할 수 있을 것으로 사료된다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.175-178
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• 2000

본 연구에서는 CDMA단말기용 Receiver MMIC를 설계하였다. 전체회로는 저잡음 증폭기, 하향 주파수 혼합기 그리고 중간주파수 증폭기로 구성된다. 또한 문턱전압과 전원전압의 변화에 대해 회로의 안정성을 높이는 바이어스 보상회로를 추가하였다. 설계시 높은 선형성과 저잡음 특성을 가지도록 토폴리기를 구성하였고 설계 결과 전체 이득은 28.5dB, 저잡음 증폭기의 입력IP3는 8dBm, 하향주파수 혼합기의 입력 IP3는 0dBm이며 전체회로의 소모전류는 22.1mA이다. 레이아웃된 전체회로의 크기는 1.4$\times$1.4 [$\textrm{mm}^2$] 이다.

• Aerospace Engineering and Technology
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• v.9 no.2
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• pp.176-184
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• 2010

The power simulator for a LEO satellite is a useful tool to analyze mission validity and energy balance for various mission scenarios by estimating power generation, power consumption, depth of discharge, bus voltage, charging/discharging current, etc. In this paper, it is described the calculation algorithm of the solar array (SA) power, the satellite load power and the battery modeling method to develop a satellite power simulation. To simulate the SA power generation, three different operation modes (DET, MPPT, CV) of SAR (Solar Array Regulator) are considered with a SA model. The satellite load power is estimated using the satellite unit power database, the unit on/off configuration at some satellite operation modes. The bus voltage and battery charging/discharging current at the specific DoD (Depth of Discharge) are calculated based on the battery characteristics. By this satellite power simulator, it can be conveniently analyzed the energy balance and the validity of a planned mission of a LEO satellite.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.6
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• pp.34-42
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• 2011

With the progress of USN technology, fields to which wireless sensor node is applicable are increased under a condition that it holds a lot of problems to solve for betterment. One of the problems which acts as an obstacle to USN industry diffusion is the wireless sensor node battery exchange to their individual life cycle. Exchanging the battery of so many sensor nodes one by one requires a great deal of times and costs. Such problem is against the convenience supply -aim by applying USN technology. In this paper, using RF wireless power transmission system that power transmission / harvesting module from a distance of 5 m and the power of 10 dBm with a current of 1 mA or more for Sensor Nodes in lithium-polymer battery charging system tested and verified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.28-36
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• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.39-45
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• 2011

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.784-794
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• 1996

In this papre, the design and the fabrication of the surface mountable voltage controlled oscillator is described for local oscillator in PCS(WACS/TDMA) handset. The VCO employs two silicon bipolar transistors of $f_{gamma}$ of 4 GHz as active devices. These are asembled to form the VCO on the 4 layer PCB of the size $12{\times}10mm$which provides the strip line resonator at the third layer. The fabricated VCO shows tuning rage over 50 MHz, phase noise -100 dBc/Hz at the 100 kHz frequency offset, and 0 dBm output power with the consumption of 22 mA at 3V. It is belived that the size will be more reduced by employing 1005 chip components and that the current consumption will be improved by employing transistors of higher $f_{gamma}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.527-530
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• 2016

This paper presents curvature-compensated reference circuits operating under low-voltage condition and achieving low-power consumption with $0.35-{\mu}m$ standard CMOS process. The proposed circuit can operate under less than 1-V supply voltage by using MOS transistors operating in weak-inversion region. The simulation results shows a low temperature coefficient by using the proposed curvature compensation technique. It generates a graph-shape temperature characteristic that looks like a sine curve, not a bell-shape characteristic presented in other published BGRs without curvature compensation. The proposed circuits operate with 0.9-V supply voltage. First, the voltage reference circuit consumes 176nW power and the temperature coefficient is $26.4ppm/^{\circ}C$. The current reference circuit is designed to operate with 194.3nW power consumption and $13.3ppm/^{\circ}C$ temperature coefficient.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1347-1353
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• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.