• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.63-70
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• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1073-1081
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• 2005

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1602-1609
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• 1998

In this paper, the design and implementation of the novel RF front end circuit for CDMA based PCS phone is described. This novel scheme is realized by building the power amplifier module combined with duplexer. The dielectric filters which are parts of duplexer are broken up and relocated into the module. Electromagnetic analysis for via holes and coupling between narrow transmissio lines is icluded to design a circuit. The combined moule has been minimaturized to be as small as 1.5CC. It has satisfied IS-95 requirements for linearity performances of CDMA signal at 24-dBm output power as well as played apart as a duplexer. The operating current of about 95mA has been saved owing to both rearranging dielectric filters and limiting operating point to class-B by considering real working power range of CDMA phones.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.1
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• pp.153-162
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• 2018

The importance of energy harvesting technique is increasing due to the elevated level of demand for sustainable power sources for wearable device applications. In this study, we developed an Energy Harvesting wearable Platform(EH-P) architecture which is used in the design of a multi-energy source based on TENG. The proposed switching circuit produces power with higher current at lower voltage from energy harvesting sources with lower current at higher voltage. This can powers microcontrollers for a short period of time by using PV and TENG complementarily placed under hard conditions for the sources such as indoors. As a result, the whole interface circuit is completely self-powered with this makes it possible to run of sensing on a Wearable device platform. It was possible to increase the wearable device life time by supplying more than 29% of the power consumption to wearable devices. The results presented in this paper show the potential of multi-energy harvesting platform for use in wearable harvesting applications, provide a means of choosing the energy harvesting source.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.52-57
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• 2011

This paper presents a 4-channel optical transmitter circuit realized in a $0.18{\mu}m$ CMOS technology for high-speed digital interface. Particularly, the VCSEL driver exploits the feed-forward technique, and the pre-amplifier employs the pulse-width control. Thus, the optical transmitter operates at the bias current up to 4mA and the modulation current from $2{\sim}8mA_{pp}$. with the pulse-width distortion compensated effectively. The 4-channel optical transmitter array chip occupies the area of $1.0{\times}1.7mm^2$ and dissipates 35mW per channel at maximum current operations from a single 1.8V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5838-5842
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• 2011

The study mainly aims to explore how deterioration of motor control center, namely MCC, and vibration put impact on temperature of bus bar as well as temperature change of bolt-nut joint. The motor control center consists of three internal parts (i.e. R, S, T) which are for motor operation of high capacity. Two dimensional mechanism for measuring temperature was designed and manufactured with infrared temperature sensor. Installing it in inner motor control center enabled researcher to monitor temperature of bus bar as well as amount of change of current regularly. Temperature change of bus bar according to load was primarily examined based on a bolted joint in the experiment. It was clearly verified that temperature change of bus bar was proportional to current consumption. Therefore, installing non-contact two dimensional mechanism for measuring temperature in motor control center would be expected to prevent temperature rise owing to overload current and power outage as well as fire accident which can be triggered by poor electrical contact.

• Applied Biological Chemistry
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• v.28 no.4
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• pp.271-277
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• 1985

A polarograph with specially designed cell compartment usable in kinetic study of the mitochondrial respiration of a small sized sample was made, and its performance and experimental conditions were examined. An applied potential (ca-1.2V vs. SCE) which gives rise to the second step reduction of oxygen caused a considerable level of a residual current independent of oxygen, which is temporarily interpreted as the reduction current of the membrane-bound redox material(s) of mitochondria. A potential corresponding to the first slop reduction of oxygen (ca-0.4V vs SCE) did not produce the residual current. Thus, it is suggested that a measurement of oxygen concentration in a sample of mitochondria and submitochondrial particles by using dropping mercury electrode should be done with an applied potential of about -0.4V vs SCE. Consumption of oxygen by mitochondria was observed to follow practically zero order kinetics. Its rate constant exhibited the proportional relationship with the respiratory activity of mitochondria. Usefulness of tile instrument was properly demonstrated in the work on the temperature effect on the respiration of mitochondria isolated from several plant 4issues which were selected on the basis of chilling susceptivity.