• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.6
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• pp.492-498
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• 2012

Characteristics of DBD(Dielectric Barrier Discharge) plasma actuator as design parameters were investigated for plasma flow control. Flow velocity and power consumption of the DBD plasma actuator were measured according to the design parameters such as discharge voltage and frequency, gap, width and length of electrode, and the thickness of dielectric barrier. The flow velocity and power consumption increased as the discharge voltage and frequency increased. As the electrode gap increased, the flow velocity increased with decreasing the power consumption, whereas high voltage was required for the plasma discharge. The flow velocity increased as the upper-electrode width decreased, and as the lower-electrode width increased at the constant power consumption. The performance of the DBD plasma actuator can be estimated at the given discharge and geometry conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1596-1602
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• 2021

Battery-operated IoT devices in IoT systems require low power consumption. In general, IoT devices enter a sleep state synchronously to reduce power consumption. A problem arises when an IoT device has to handle asynchronous user requests, as the duty cycle must be reduced to enhance response time. In this paper, we propose a new low-power-consumption scheme, called Repetitive Wake-up scheme for IoT systems of asynchronous environments such as indoor lights control. The proposed scheme can reduce power consumption by sending wake-up signals from the smartphone repetitively and by retaining the IoT device in sleep state to the smallest possible duty cycle. In the various environments with IoT devices at home or office space, we showed that the proposed scheme can reduce power consumption by up to five times compared to the existing synchronous interlocking technique.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.451-454
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• 2007

오늘날 많은 임베디드 시스템이 배터리를 통해 전력을 공급한다. 이처럼 제한적인 배터리 용량 때문에 임베디드 소프트웨어는 개발 시에 전력소비를 고려하여 디자인하여야 한다. 이와 같은 이유로 최근 저전력 디자인과 소프트웨어 소비전력 분석 및 분석에 대한 연구가 두드러지게 진행되고 있다. 측정 기반 전력 소모 분석 기법의 대표적인 부류인 명령어 수준 전력 분석 기법이 CPU와 메모리의 전력 소비만을 고려하는 점을 보안하기 위하여 본 논문에서는 시스템 전체의 소비 전력을 분석하기 위하여 이벤트 방식의 전력 소모 분석 기법을 제안한다. 사용자는 소비전력을 모니터링하고 싶은 코드 구간에 대해 이벤트로 지정하고 해당 이벤트가 발생하는 동안 소비되는 전력을 DAQ 장비로부터 측정한 후 결과를 바탕으로 소프트웨어의 수행시간, 소비전력량, 전력소비 병목현상, 커널 이벤트의 발생 빈도 및 횟수 등을 파악하여 소프트웨어의 성능을 계층적으로 분석할 수 있는 데이터를 제공한다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.227-233
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• 2000

In this paper, we present a new high-level data path synthesis algorithm which solves the two design problems, namely, scheduling and allocation, with power minimization as a key design parameter. From the observations in previous works on data path synthesis for low power, we derive an integer programming (IP) formulation for the problem, from which we then develop an efficient heuristic to carry out the scheduling and allocation simultaneously. Our experimental results demonstrate that the proposed algorithm is very effective in saving power consumption of circuits significantly.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.37-48
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• 2005

The efficiency of power supply circuits such as DC-DC converters and batteries varies on the trend of the power consumption because their efficiencies are not fixed. To analyze the efficiency of power supply circuits, we need the temporal behavior of the power consumption of the loads, which is dependent on the activity factors of the devices during the operation. Since it is not easy to model every detail of those factors, one of the most accurate power consumption analyses of power supply circuits is measurement of a real system, which is expensive and time consuming. In this paper, we introduce an active load emulator for embedded systems which is capable of power measurement, logging, replaying and synthesis. We adopt a pattern recognition technique for data compression in that long-term behaviors of power consumption consist of numbers of repetitions of short-term behaviors, and the number of short-term behaviors is generally limited to a small number. We also devise a heterogeneous structure of active load elements so that low-speed, high-current active load elements and high-speed, low-current active load elements may emulate large amount and fast changing power consumption of digital systems. For the performance evaluation of our load emulator, we demonstrate power measurement and emulation of a hard drive. As an application of our load emulator, it is used for the analysis of a DC-DC converter efficiency and for the verification of a low-power frequency scaling policy for a real-time task.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.389-390
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• 2017

본 논문은 전압형 HVDC 시스템의 기술 동향에 대하여 설명하고 있다. 전압형 HVDC 시스템은 무효전력소모가 있고, 전류형 HVDC 시스템은 무효전력 소모가 없기 때문에 시스템의 구성과 제어에 많은 차이를 보이고 있다. 본 논문은 이러한 현황을 요약 정리한 논문이다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.688-690
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• 2002

고성능 슈퍼스칼라 프로세서에서는 명령어 수준 병렬성(Instruction Level Parallelism, ILP)의 장애인 명령어간의 종속 관계 중 데이터 종속관계를 극복하기 위해 값 예측기를 이용하여 모험적으로 명령어들을 실행한다. 값 예측 시에 필요한 테이블 참조와 값 예측 실패 시 실행되는 잘못된 명령어의 실행은 프로세서의 부가적인 전력 소모를 요구한다. 본 논문에서는 값 예측기와 Cai-Lim의 전력모델을 슈퍼스칼라 프로세서 사이클 수준 시뮬레이터인 SimpleScalar 3.0 툴셋에 삽입하여 전력 소모량을 측정하고 분석한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.42-50
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• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.76-83
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• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.