• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.05a
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• pp.153-156
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• 2009

본 논문에서는 어드레스 구간에서 벽전압 손실을 발생시키는 원인을 분석하고, 특히 어드레스 구간에서 각 전극간의 다양한 전위 조건이 어드레스 방전 지연 시간에 미치는 영향을 조사하였다. 실험 결과를 통하여 벽전압 손실은 전극간의 셀 전압이 동시 방전점에서 비방전 영역으로 이동한 조건에서는 영향을 받지 않지만, 전극간의 셀 전압이 방전 개시 전압의 조건에서는 큰 영향을 받게 되는 것을 확인하였다. 특히, XY 전극간의 전위조건에 의한 벽전압 손실보다는 AY 전극간의 전위 조건에 의한 벽전압 손실이 어드레스 방전 지연 시간 특성을 저해하는 주요한 원인임을 확인하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.2
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• pp.187-193
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• 2004

For a power source of usual electronic devices such as PDA, smart phone, UPS and electric vehicle, the battery made of serially connected multiple cells is generally used. In this case, if there are some unbalanced among cell voltages, the total lifetime and the total capacity of the battery are limited to a lower value. To maintain a balanced condition in cells, an effective method of regulating the cell voltage in indispensable. In this paper, we propose the design of a balancing circuit for electronic appliances. The balancing system was controlled by a micro-controller which enables to implement the balancing action during charging period. Proposed method has been verified by the experiment using the charger and recorder. The experimental results show that the individual battery equalization can improve battery capacity and battery lifetime and performance through an extended operational time.

• Journal of IKEEE
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• v.23 no.2
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• pp.524-528
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• 2019

Although different types of discharge cells exist, in common it is the primary goal for all discharge cells to have lower drive voltages and higher efficiency characteristics. To improve these factors, many studies are conducted that prolong the discharge path inside the discharge cell or change the composition of the working gas. In this paper, the two-dimensional fluid simulation was used to calculate the discharge voltage (firing voltage and sustain voltage) and the change in luminance and luminous efficacy according to the change in gap distance between discharge electrodes. In addition, we looked at changes in various charged particles, exciting particles and VUV particles, and studied the causes of the resulting values.

• Korean Journal of Optics and Photonics
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• v.5 no.3
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• pp.411-417
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• 1994

The electro-optic polarization transmission characteristics of a liquid crystal (LC) cell is represented by a rotational transformation on the Poincare sphere, and its characteristic parameters, the angle and the axis of the rotation, are experimentally determined with respect to the voltage applied to the LC cell. From the experimental data obtained, we determine driving voltage for the LC cell to give the rotation angle near $180^{\circ}$ of the rotation for the change of the state of the LC cell from non-select to select state, which is a necessary condition for the realization of maximally bright images. The directions of the transmission axes of the polarizer and the analyzer which form a liquid crystal display panel together with the LC cell, are determined from the general characteristics of the rotaional transformation of the LC cell. cell.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.125-125
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• 2011

Silicon-oxide-silicon nitride-oxide silicon (SONOS) 구조를 가진 플래쉬 메모리 소자는 기존의 floating gate (FG)를 이용한 플래쉬 메모리 소자에 비해 구동 전압이 낮고, 공정 과정이 간단할 뿐만 아니라 비례 축소가 용이하다는 장점 때문에 차세대 플래쉬 메모리 소자로 많은 연구가 진행되고 있다. SONOS 구조를 가진 플래쉬 메모리에서 소자의 셀 사이즈가 감소함에 따라 발생하는 인접한 셀 간의 간섭 현상에 대한 연구가 소자의 성능 향상에 필요하다. 본 연구에서는 SONOS 구조를 가진 플래쉬 메모리에서 소자의 셀 사이즈가 작아짐에 따라 발생하는 인접한 셀 간의 간섭 현상에 대해 recess field 의 깊이에 따른 변화를 조사하였다. 게이트의 길이가 30nm 이하인 SONOS 구조를 가진 플래쉬 메모리 소자의 구조에서 recess field의 깊이의 변화에 따른 소자의 전기적 특성을 삼차원 시뮬레이션 툴인 sentaurus를 사용하여 계산하였다. 커플링 효과를 확인하기 위해 선택한 셀의 문턱전압이 주변 셀들의 프로그램 상태에 미치는 영향을 관찰하였다. 본 연구에서는 SONOS 구조를 가진 플래쉬 메모리에서 셀 사이에 recess field 를 삽입함으로 인접 셀 간 발생하는 간섭현상의 크기를 줄일 수 있음을 시뮬레이션 결과를 통하여 확인하였다. 시뮬레이션 결과는 recess field 깊이가 증가함에 따라 인접 셀 간 발생하는 간섭현상의 크기가 감소한 반면에 subthreshold leakage current가 같이 증가함을 보여주었다. SONOS 구조를 가진 플래쉬 메모리 소자의 성능향상을 위하여 recess field의 깊이를 최적화 할 필요가 있다.

• Korean Chemical Engineering Research
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• v.51 no.3
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• pp.370-375
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• 2013

We analyze the effects of CO poisoning and air bleeding on the performance of a PEM (polymer electrolyte membrane) fuel cell stack fabricated using commercial MEA (membrane electrode assembly). Dynamic response data from the experiments on the performance of a stack are identified by obtaining steady-state gains and time-constants of the first-order system model expressed as a first-order differential equation. It is found that the cell voltage of the stack decreases by 1.3-1.6 mV as the CO concentration rises by 1 ppm. The time elapsed to reach a new steady state after a change in the CO concentration is shortened as the magnitude of the change in the CO concentration increases. In general, the steady-state gain becomes bigger and the time-constant gets smaller with increasing the air concentration (air-bleeding level) in the reformate gas to restore the cell voltage. However, it is possible to recover 87%-96% of the original cell voltages, which are measured with free of CO, within 1-30 min by introducing the bleed air as much as 1% of the reformate gas into the stack.

• Journal of IKEEE
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• v.23 no.1
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• pp.1-8
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• 2019

In this paper, the electrical characteristics with various C-rates are tested with a high power series battery pack comprised of 18650 cylindrical nickel cobalt aluminum(NCA) lithium-ion battery. The electrical characteristics of discharge capacity test with 14S1P battery pack and electric vehicle (EV) cycle test with 4S1P battery pack are compared and analyzed by the various of C-rates. Multiple linear regression is used to estimate voltage imbalance of 14S1P and 4S1P battery packs with various C-rates based on experimental data. The estimation accuracy is evaluated by root mean square error(RMSE) to validate multiple linear regression. The result of this paper is contributed that to use for estimating the voltage imbalance of discharge capacity test with 14S1P battery pack using multiple linear regression better than to use the voltage imbalance of EV cycle with 4S1P battery pack.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.464-466
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• 2007

H-Bridge Multi-Level (HBML) 고압인버터는 저압의 반도체 소자를 사용하는 단상 H-Bridge 인버터로 구성 된 셀을 직렬로 연결함으로써 정현파에 가까운 고전압을 얻을 수 있고, 입 출력 고조파가 낮아서 필터가 필요 없는 토폴로지로 산업분야에서 사용이 확대되고 있다. 본 논문은 HBML 고압인버터의 마스터 제어기와 셀 제어기의 통신 하드웨어를 병렬로 구성하여서 하나의 전압지령 값과 Angle 값으로 셀에서 PWM을 구현 할 수 있는 분산제어 방식을 제안한다. 이 방식에서 셀 제어기가 전압, 전류, 주파수, 보호기능, 통신감시 정보 등 셀 제어의 대부분을 담당함으로써 마스터 제어기의 부담을 줄이고, 따라서 신호선의 개수를 줄일 수 있다. 또 통신하드웨어의 종단에 마스터 제어기를 연결만 하면 마스터제어기의 2중화가 가능하므로 사용하고 있던 마스터 제어기의 고장 발생 시에 대체하여 사용할 수 있으므로 시스템의 안정성 향상에 도움을 준다. 선간전압 33레벨로 구성된 HBML 고압인버터 시험을 통해 제안된 방식의 타당성과 신뢰성을 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.93-98
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• 2004

A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$. It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K${\times}$32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.