• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.8
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• pp.637-642
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• 2014

In this paper, we propose a efficient shift index searching algorithm for design of the block LDPC codes. It is combined with the message-passing based cycle search algorithm and ACE algorithm. We can determine the shift indices by ordering of priority factors which are effect on the LDPC code performance. Using this algorithm, we can construct the LDPC codes with low complexity compare to trellis-based search algorithm and save the memory for storing the parity check matrix.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.2
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• pp.106-116
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• 1998

A position control algorithm of a flexible manipulator is studied. The proposed algorithm is based on an ACFAC(Automatic Constructed Fuzzy Adaptive Controller) system based on the neural network learning algorithms. The proposed system learns membership functions for input variables using unsupervised competitive learning algorithm and output information using supervised outstar learning algorithm. ACFAC does not need a dynamic modeling of the flexible manipulator. An ACFAC is designed that the end point of the flexible manipulator tracks the desired trajectory. The control input to the process is determined by error, velocity and variation of error. Simulation and experiment results show a robustness of ACFAC compared with the PID control and neural network algorithms.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.625-634
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• 2002

Cryptography is the methods of making and using secret writing that is necessary to keep messages private between two parties. Cryptography is compute-intensive algorithm and needs cpu resource excessively. To solve these problems, there exists hardware approach that implements cryptographic algorithm with hardware chip. In this paper, we presents the design and implementation of cryptographic hardware and compares its performance with software cryptographic algorithms. The experimental result shows that the hardware approach causes high I/O overheads when it transmits data between cryptographic board and host cpu. Hence, low complexity cryptographic algorithms such as DES does not improve the performance. But high complexity cryptographic algorithms such as Triple DES improve the performance with a high rate, roughly from two times to Sour times.

• The Journal of Information Technology
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• v.5 no.4
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• pp.73-79
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• 2002

In this paper, I will propose the Niche-Meta Genetic Algorithm that has a multi-mutation operator for design of fuzzy controller. The gene in the proposed algorithm is formed by several parameters that represent the crossover rate, mutation rate and input-output membership functions. The optimization of fuzzy membership function is performed with local search on sub-population and the optimal structure is constructed with global search on total-population. The multi-mutation is selected under basis of the result of local evolution. A simulation for 2 D.O.F wheeled-mobile robot is showed to prove the efficiency of the proposed algorithm

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2555-2562
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• 2009

The algorithm that is proposed in this paper defined a probability function to count connection process and connection-end process to apply TRW algorithm to voice network. Set threshold to evaluate the algorithm that is proposed, Based on the type of connection attack traffic changing the probability to measure the effectiveness of the algorithm, and Attack packets based on the speed of attack detection time was measured. At the result of evaluation, proposed algorithm shows that DDoS attack starts at 10 packets per a second and it detects the attack after 1.2 seconds from the start. Moreover, it shows that the algorithm detects the attack in 0.5 second if the packets were 20 per a second.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2690-2700
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• 1997

This paper presents parallel sorting algorithm, SHARED-MEMORY-BS and REDUCED-BS, which are implemented on shared-memory parallel computers. These algorithm sort N keys in $O(log^2N)$ time. REDUCED-BS users a parity strategy which gives an idea for the efficient usage of the local memory associated with each processor. By taking advantage of the local memory associated with each processor, the communication of REDUCED-BS is decreased by approximately half that of SHARED-MEMORY-BS. On the basis of alleviating the communication, the algorithm REDUCED-BS results in a significant improvement of performance.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.06a
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• pp.115-120
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• 2002

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.67-68
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• 2013

저가형 저전력 LED 구동회로에서는 종종 직렬 저항을 이용한 전류 밸런스 회로를 사용한다. 이러한 회로에서 밸런싱 저항은 양산시 생기는 LED 순방향 전압의 편차에 관계없이 LED 스트링간의 전류 밸런싱을 유지시키는 역할을 한다. 본 논문에서는 직렬 저항의 공칭값과 공급 전압값을 최적설계 하기위한 효과적인 설계 알고리즘을 제안한다. 제안한 알고리즘은 몬테카를로 기법을 사용하여 순방향 전압의 통계적인 산포와 직렬저항 소자의 상용값 및 공차를 동시에 고려하고, 비용함수를 도입하여 회로 최적화를 진행한다. 기존의 설계 방법 대비 성능 개선 정도를 구체적인 설계사례를 통해 비교 분석함으로써 제안 방법을 검증한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.2
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• pp.276-283
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• 1994

Using a neural network for vector quantization, we can expect to have better codebook design algorithm for its adaptive process. Also, the designed codebook puts the codewords in order by its self-organizing characteristics, which makes it possible to partially search the codebook for real time process. To exploit these features of the neural network, in this paper, we propose a new codebook design algorithm that modified the KSFM(Kohonen`s Self-organizing Feature Map) and then combines the K-means algorithm. Experimental results show the performance improvment and the ability of the partical seach of the codebook for the real time process.

• The Journal of the Acoustical Society of Korea
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• v.17 no.3
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• pp.17-26
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• 1998

이 논문은 사운드 합성을 위한 전용 DSP의 설계에 관한 내용이다. 설계된 음원 DSP는 사운드 카드나 전자 악기, 혹은 노래방 기기 등에서 미디 신호를 입력으로 받아서 사운드를 합성하는데 사용된다. 합성 알고리즘으로는 FM방식과 PCM방식을 지원하며, 구조 가 다르고 합성 방식이 서로 다른 8개의 알고리즘을 하드웨어적으로 구현하였다. 설계된 DSP는 44.1KHz의 16비트 출력으로 32개의 음을 동시에 낼 수 있다. DSP 내부 구조의 최 적화와 마이크로 동작의 병렬화를 통해 실제 필요한 주파수보다 낮은 주파수에서 동작시킴 으로써 전력 소모와 칩 구현에서 많은 이점을 가져올 수 있었다. 설계된 DSP는 COMPASS 툴에서 0.8㎛ 표준 셀로 합성되어 칩으로 제작되었으며, 동작 주파수는 33MHz이다. 제작된 칩을 검증하기 위해 PC에 삽입되는 음원 모듈 카드를 제작하여 미디 음악을 연주시켜 보았 다. 그 결과 원하는 동작 주파수에서 완벽하게 사운드를 합성해내는 것을 확인할 수 있었다.