• Journal of KIISE
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• v.43 no.7
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• pp.820-826
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• 2016

There is a growing requirement for big data processing which extracts valuable information from a large amount of data. The Hadoop system employs the MapReduce framework to process big data. However, MapReduce has limitations such as inflexible and slow data processing. To overcome these drawbacks, SQL query processing techniques known as SQL-on-Hadoop were developed. Apache Tajo, one of the SQL-on-Hadoop techniques, was developed by a Korean development group. External merge sort is one of the heavily used algorithms in Tajo for query processing. The performance of external merge sort in Tajo is influenced by two parameters, sort buffer size and fanout. In this paper, we analyzed the performance of external merge sort in Tajo with various sort buffer sizes and fanouts. In addition, we figured out that there are two major causes of differences in the performance of external merge sort: CPU cache misses which increase as the sort buffer size grows; and the number of merge passes determined by fanout.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11b
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• pp.1197-1200
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• 2003

USIM(Universal Subscriber Identity Module) 기술은 데이터의 관리와 보호를 하나의 소형 칩 내에 집약시킨 기술로 최근에 이 기술에 대한 관심도가 증가하고 있다. 자바카드 가상기계는 자바 언어로 작성된 프로그램이 USIM 칩 내부에서 실행 가능하도록 해준다. 하지만 자바카드 가상 기계는 자원 제약적인 디바이스의 특성으로 인하여 검증기술을 제공하지 않는다. 본 논문에서는 정적 체크 기반의 효율적인 바이트코드 검증기를 제안한다. 연구 결과 본 논문에서 제안하는 검증기는 일반적인 것에 비해 90% 이상의 사이즈가 감소되었다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.70-76
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• 2011

LTE Re1-10 aims at peak. data rates of 1Gbits/s for the downlink and 500 Mbits/s for the uplink, which can be accomplished by not only wide spectrum but also advanced MIMO techniques such as precoded MIMO and cooperative relays. Considering some relays can have more direct signal paths than mobile stations do, LoS components are examined to build more efficient codebooks for Rician channels. The proposed codebooks perform better than the existing LTE codebooks as the criterium of LoS, K-factor increases. Conserving the advantages and max-min chordal distance of the existing LTE codebooks, the proposed ones also maximize the minimum chordal distances between codewords over Rician fading channels. Link-level simulation with LTE system parameters confirm the performance improvements as the value of K increases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.306-313
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• 2007

In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).

• Journal of the Korea Society of Computer and Information
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• v.15 no.7
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• pp.99-108
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• 2010

For effective maintenance for web applications, it is necessary to improve the readability of the source pages. Though CSS(Cascading Style Sheet) belongs to pure presentation layer in various web constituent entities, CSS codes are often used by inlning and they are sometimes automatically generated by web development tools. The existing studies on CSS optimization have only focused on reducing the size of codes and they did not incorporate the readability or the reusability. In this paper, CSS codes are structured and several criteria for readability are defined to improve the readabilty and reusability. Based on them, the algorithm to improve the readability are proposed. Finally, case study are presented to show the applicability of the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1301-1306
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• 2011

RTOS in the embedded system is a powerful tool for the design of multi-tasking. However, previous RTOS has large proportion in the MCU with limited memory. So it is difficult to apply RTOS. In this paper, I removed less frequently used features from the traditional RTOS, and designed lightweight RTOS that schedules and manages the resources with minimal code. I used techniques to obtain user memory using sharing stack, and to reduce the overhead at context. Considering ratio of kernel and applications, the RTOS designed in this paper is available on the MCU with more than 4KB of program memory.

• Journal of IKEEE
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• v.15 no.4
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• pp.293-298
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• 2011

In the paper, we propose a new CMF(Constant Modulus Fourth) algorithm for WCDMA(Wideband Code Multiple Access) RF(Radio Frequency) Repeater. CMF algorithm is proposed by modifying the CMA(Constant Modulus Algorithm) algorithm and improved performances are achieved by properly adjusting step size values. The steady state MSE(Mean Square Error) performance of the proposed CMF algorithm with step size of 0.35 is about 4dB better than that of the conventional CMA algorithm. And the proposed CMF algorithm requires 400~1100 less iterations than the LMS(Least Mean Square) and NLMS(Normalized Least Mean Square) algorithms at MSE of -25dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.1
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• pp.7-16
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• 2004

The tool path needs to be determined in an efficient manner to generate the final NC (numerical control) code for efficient machining. This is particularly important in machining free form pockets with an arbitrary wall geometry on a three-axis CNC machine. Many CAD/CAM systems use linear interpolation to generate NC tool paths for curved surfaces. However, this needs to be modified to improve the smoothness of the machined bottom surface, reduce machining time and CL (cutter location) file size. Curved machining can be a solution to reduce these problems. The unified rough and finish cut algerian and the tool motion is graphically simulated. In this paper, a grid based 3D navigation algorithm for generating NC tool path data for both linear interpolation and a combination of linear and circular interpolation for three-axis CNC milling of general pockets with sculptured bottom surfaces is developed.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.394-396
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• 2004

CE 제품에 리얼타임 OS를 도입하면서, 제품의 조건을 만족시키기 위한 기술에 대해 많은 연구가 진행되고 있다. 특히, CE 제품에 있어서 중요한 이슈인 부팅 시간은 펌웨어수준과 비교했을 때 코드사이즈나 OS 초기화 과정 때문에 다소 느려지는 경향을 보이고 있다. 본 논문은 이러한 CE 제품의 부팅 시간에 초점을 맞추고 리얼타임 OS 적용시의 부팅 시간을 개선하였다. 구현에 사용된 ARM920T Core는 32-비트 RISC 구조이며, 각 16KB의 인스트럭션 Cache와 데이터 Cache, 그리고 MMU(Memory Management Unit)로 구성되어 있으며, 리얼타임 OS는 선점형 방식의 커널로 구성된 OS를 사용하였다.