• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.743-746
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• 2005

본 논문에서는 디지털 비디오 인코딩 과정의 VLC(variable length coding) 영역에서 블록계층의 DC/AC 성분을 이용한 인증과 서명의 이중 비디오 워터마킹 시스템을 제안하였다. 제안한 기법은 블록계층의 DC 성분과 AC 성분에서 HVS(human visual system)의 특성을 고려한 것이다. 인증 워터마킹은 주요한 정보를 포함하는 저주파 영역과 윤곽선 정보를 포함하는 중간 주파수 영역을 이용하여 인트라 프레임의 DC 성분과 움직임 벡터의 부호를 변형시켰고, 서명 워터마킹은 모든 프레임의 AC 성분들 중에서 마지막 AC 성분의 Level이 '1'인 경우에만 워터마크를 삽입하였다. 서명 워터 마크 검출은 저작권자의 비밀 키에 의해서만 가능하고, 기술적인 면에서 저자권자의 판별 기준이 될 수 있다. 제안한 이중 비디오 워터마킹 시스템의 특징은 인증과 서명의 두 가지 기능을 선택적으로 수행할 수 있으며, 계산과정이 복잡하지 않으면서 비트 스트림(bit-stream)을 유지시킨다. 그리고 실험 결과에서 기존의 방법보다 화질 면에서 $2{\sim}3dB$ 더 높은 수치를 얻어 우수함을 보였고, 인코딩 수행 속도에 미치는 영향은 거의 없었으며, 향후 실시간 인코딩 처리에 응용될 수 있다.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.6
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• pp.1-7
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• 2017

This Paper Addresses a Performance Enhancement of Multitude Receivers Communicating with a Basestation. A General Link between Basestation and Terminal is that a Basestation is connected with Multitude Receivers and Time, Frequency and Code are shared and used among them. We propose an Algorithm of Enhancing Receiver Capability at the Receiver when access Point of Acting as a Basestation in this Environment Modifies Transmission Data Separately to be sent. In the Proposed Algorithm, we configure Transmit Data to Use Maximal Ratio Combining Technique in the Receiver, and Estimate Transmitter Signal per Each Receiver and Simulate Bit Error Rate and Show the Performance Results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1005-1015
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• 1999

This paper is concerned with an improvement on IFFT (inverse fast Fourier transform) and FFT based baseband digital implementation algorithm for BPSK (binary phase shift keying)-modulated MC-CDMA (multicarrier-code division multiple access) systems, that is functionally equivalent to the conventional implementation algorithm, while reducing computational complexity and bandwidth requirement. We also derive an equalizer structure for the proposed implementation algorithm. The proposed algorithm is based on a variant of FFT algorithm that utilizes a N/2-point FFT/IFFT for simultaneous transformation and reconstruction of two N/2-point real signals. The computer simulations under additive white Gaussian noise channels and frequency selective fading channels using equal gain combiner and maximal ratio combiner diversities, demonstrate the performance of the proposed algorithm.

• Journal of the Korea Society of Computer and Information
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• v.11 no.5 s.43
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• pp.267-272
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• 2006

In this paper, an integrated and small Ka-band transceiver module has been developed for measuring distance at the radar systems. Oscillator of cavity type, The MMIC such as VCO, power amplifier, LNA, and mixer, and passive components are integrated on carriers and these are assembled in the transceiver module directly. The test result shows the output power of 21dBm and the noise figure of 5dB using developed transceiver module. Using developed FMCW transceiver module. We can measure the 60m range target by detecting the beat frequency and distinguish both earth and sky using radiometer signal. So we defined that the integrated module using MMIC had a good performance for the radar and radiometer at Ka-band.

• Journal of Digital Convergence
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• v.10 no.11
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• pp.371-376
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• 2012

In this paper, we propose a new data coding method and its circuits for minimizing data transition in text image. The proposed circuits can solve the synchronization problem between input data and output data in the modified LVDS algorithm. And the proposed algorithm is allowed to transmit two data signals through additional serial data coding method in order to minimize the data transition in text image and can reduce the operating frequency to a half. Thus, we can solve EMI(Electro-Magnetic Interface) problem and reduce the power consumption. The simulation results show that the proposed algorithm and circuits can provide an enhanced data transition minimization in text image and solve the synchronization problem between input data and output data.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2006.05a
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• pp.119-123
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• 2006

본 논문에서는 마이크로프로세서의 기능을 수행하는 데 필수적이며 사용빈도가 높은 총 64개의 명령어를 정의한 후 이를 처리할 데이터패스를 구성해 스테이트 머쉰으로 제어하는 방식으로 실용적 8비트 마이크로프로세서를 VHDL로 설계를 하고 FPGA로 구현했다. 통상 마이크로프로세서 관련 논문에서는 기능적 시뮬레이션까지만 했거나, 인터럽트 기능이 없든지, 하드웨어로 구현을 하지 않았거나, 또는 개발 관련 내용이 자세히 제시되지 않았었다. 본 논문에서는 데이터 이동, 논리, 가산 연산뿐만 아니라 분기, 점프 연산도 실행할 수 있도록 해 연산 및 제어용도에 적합하도록 하였고, 스택, 외부 인터럽트 기능까지도 지원하도록 해 그 자체로서 완전한 실용적 마이크로프로세서가 되도록 하였다. 또한 프로그램 ROM까지도 칩 안에 넣어 전체 마이크로프로세서를 단일 칩으로 구현하였다. 타이밍 시뮬레이션으로 검증 후 제작 과정을 통해, 설계된 마이크로프로세서가 정상적으로 동작함을 확인하였다. Altera MAX+.PLUS II 통합개발환경 하에서 EP1K50TC144-3 FPGA 칩으로 구현을 하였고 최대 동작주파수는 9.39MHz까지 가능했고 사용한 로직 엘리먼트의 개수는 2813개로서 논리 사용률은 97%이었다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.4
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• pp.35-43
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• 2000

In this paper, we propose to transmit convolutionally coded DS waveforms over orthogonally overlapped subchannels. It is shown that the proposed system, the convolutionally coded orthogonal multicarrier DS/CDMA system, significantly outperforms the system using frequency diversity combining. It is also shown that the proposed system has better performance than the convolutionally coded almost non-overlapped multicarrier DS/CDMA system under the condition that the information rate and total available bandwidth are the same.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.34-41
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• 1998

In this paper, we evaluate synchronization techniques suitable for high-speed ATM satellite communications with a transmission rate of 155Mbit/s, and propose optimal algorithms that improve the tracking performance, where QPSK is selected for a modulation scheme, and the receiver is operated in burst mode. Based on these asumptions, we proposed modified algorithms and architectures for automatic frequency control(AFC), carrier recovery(CR), and symbol timing recovery(STR) for burst acquisition. Analysis is performed under AWGN environments with respect to the number of required symbol, steady-state stability, and hardware implementation for the proposed algorithms.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.53-58
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• 2007

OFDM (orthogonal frequency division multiplexing) is an effective modulation technique for high speed transmission over fading channels. However, it has a high bit error rate in the receiver if there is an error on frame synchronization because of phase rotation. A coherent OFDM system has to acquire exact timing synchronization of fraction and integer sampling positions. When a sampling offset exist the performance of a receiver will be degraded severely. In this paper, we propose an algorithm that acquires the fractional sampling offset in OFDM systems. This scheme compares the channel impulse responses with the early and late sampled signals having 0.5 sample offset from the estimated sampling positions by correlation with the received and training samples. Its performance is verified by computer simulations in multipath channels.