• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1754-1766
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• 2015

Packet classification carried out in Internet routers is one of the challenging tasks, because it has to be performed at wire-speed using five header fields at the same time. In this paper, we propose a leaf-pushed AQT bitmap trie. The proposed architecture applies the leaf-pushing to an area-based quad-trie (AQT) to reduce unnecessary off-chip memory accesses. The proposed architecture also applies a bitmap trie, which is a kind of multi-bit tries, to improve search performance and scalability. For performance evaluation, simulations are conducted by using rule sets ACL, FW, and IPC, with the sizes of 1k, 5k, and 10k. Simulation results show that the number of off-chip memory accesses is less than one regardless of set types or set sizes. Additionally, since the proposed architecture applies a bitmap trie, the required number of on-chip memory accesses is the 50% of the leaf-pushed AQT trie. In addition, our proposed architecture shows good scalability in the required on-chip memory size, where the scalability is identified by the stable change in the required memory sizes, as the size of rule sets increases.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07b
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• pp.505-507
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• 2005

인터넷의 확장에 따라 형태소 분석기에서 사용하는 사전의 규모도 커지고 있다. 이러한 상황은 사전의 증가를 가져옴으로써 기존 형태소 분석기의 자료 구조에 대한 새로운 요구를 발생시켰다. 기존의 트라이를 이용한 방법은 노드의 과다 생성과 데이터 부족문제로 발생하는 메모리 낭비의 문제를 가지고 있다. 효율적인 메모리 사용을 위해서는 해시 구조가 적절하다. 하지만 이 경우 트라이에 비해 검색 횟수의 복잡도가 비약적으로 증가되는 문제점을 안고 있다. 본 논문에서는 해시를 위한 길이 비트맵을 이용하여 검색 횟수를 제한할 수 있는 방법을 제안하였다. 실험을 통해 제안된 자료 구조와 해시와 트라이의 형태소 사전 검색 횟수를 비교하였으며 비문 사용이 많은 영역에서 효율적임을 입증하였다.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.129-142
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• 2004

As the Internet gets faster, the demand for high-speed routers that are capable of forwarding more than giga bits of data per second keeps increasing. In the previous research, Bitmap Trie algorithm was developed to rapidly execute LPM(longest prefix matching) process which is Well known as the Severe performance bottleneck. In this paper, we introduce a novel algorithm that drastically enhanced the performance of Bitmap. Trie algorithm by applying three techniques. First, a new table called the Count Table was devised. Owing to this table, we successfully eliminated shift operations that was the main cause of performance degradation in Bitmap Trie algorithm. Second, memory utilization was improved by removing redundant forwarding information from the Transfer Table. Lastly. the range of prefix lookup was diversified to optimize data accesses. On the other hand, the processing delays were classified into three categories according to their causes. They were, then, measured through the execution-driven simulation that provides the higher quality of the results than any other simulation techniques. We tried to assure the reliability of the experimental results by comparing with those that collected from the real system. Finally the Enhanced Bitmap Trie algorithm reduced 82% of time spent in previous algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3B
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• pp.339-348
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• 2004

Packet classification is an important factor to support various services such as QoS guarantee and VPN for users in Internet. Packet classification is a searching process for best matching rule on rule tables by employing multi-field such as source address, protocol, and port number as well as destination address in If header. In this paper, we propose hardware based packet classification algorithm by employing tree bitmap of multi-bit trio. We divided prefixes of searching fields and rule into multi-bit stride, and perform a rule searching with multi-bit of fixed size. The proposed scheme can reduce the access times taking for rule search by employing indexing key in a fixed size of upper bits of rule prefixes. We also employ a marker prefixes in order to remove backtracking during searching a rule. In this paper, we generate two dimensional random rule set of source address and destination address using routing tables provided by IPMA Project, and compare its memory usages and performance.

• Journal of Korea Multimedia Society
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• v.9 no.2
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• pp.244-254
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• 2006

This paper presents an efficient hybrid technique to compact the trie indexing the huge forward table small enough to be stored into cache for speeding up IP lookup. It combines two techniques, an encoding scheme called bit-map and a controlled-prefix expanding scheme to replace slow memory search with few fast-memory accesses and computations. For compaction, the bit-map represents each index and child pointer with one bit respectively. For example, when one node denotes n bits, the bit-map gives a high compression rate by consumes $2^{n-1}$ bits for $2^n$ index and child link pointers branched out of the node. The controlled-prefix expanding scheme determines the number of address bits represented by all root node of each trie's level. At this time, controlled-prefix scheme use a dynamic programming technique to get a smallest trie memory size with given number of trie's level. This paper proposes standard that can choose suitable trie structure depending on memory size of system and the required IP lookup speed presenting optimal memory size and the lookup speed according to trie level number.

• Journal of KIISE:Information Networking
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• v.30 no.2
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• pp.282-292
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• 2003

This paper proposes an efficient data structure for forwarding IPv4 and IPv6 packets at the gigabit speed in backbone routers. The LPM(Longest Prefix Matching) search becomes a bottleneck of routers' performance since the LPM complexity grows in proportion to the forwarding table size and the address length. To speed up the forwarding process, this paper introduces a data structure named BMT(Bit-Map Tie) to minimize the frequent main memory accesses. All the necessary search computations in BMT are done over a small index table stored at cache. To build the small index table from the tie representation of the forwarding table, BMT represents a link pointer to the child node and a node pointer to the corresponding entry in the forwarding table with one bit respectively. To improve the poor performance of the conventional tries when their height becomes higher due to the increase of the address length, BMT adopts a binary search algorithm for determining the appropriate level of tries to start. The simulation experiments show that BMT compacts the IPv4 backbone routers' forwarding table into a small one less than 512-kbyte and achieves the average speed of 250ns/packet on Pentium II processors, which is almost the same performance as the fastest conventional lookup algorithms.

• Journal of KIISE:Information Networking
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• v.28 no.2
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• pp.262-276
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• 2001

Recently much research for developing forwarding table that support fast router without employing both special hardware and new protocols. This article introduces a new forwarding data structure based on the software to enable forwarding lookup to be penormed at giga-bit speed. The forwarding table is known as a bottleneck of the routers penormance due to its high complexity proportional to the forwarding table size. The recent research that based on the software uses a Patricia trie and its variants. and also uses a hash function with prefix length key and others. The proposed forwarding table structure construct a forwarding table by the bit stream array in which it constructs trie from routing table prefix entries and it represents each pointer pointing the child node and the associated forwarding table entry with one bit The trie structure and routing prefix pointer need a large memory when representing those by linked-list or array. but in the proposed data structure, the needed memory size is small enough since it represents information with one bit. Additionally, by use a lookup method that start searching at desired middle level we can shorten the search path. The introduced data structure. called bit-map trie shows that we can implement a fast forwarding engine on the conventional Pentium processor by reducing the backbone routing table fits into Level 2 cache of Pentium II processor and shortens the searching path. Our experiments to evaluate the performance of proposed method show that this bit-map trie accomplishes 5.7 million lookups per second.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.329-330
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• 2000

기가비트 속도를 지원하는 고속 라우터의 IP 주소 검색은 소프트웨어로 구현할 수 없다는 일부의 믿음과는 달리 소프트웨어만으로도 고속 IP 주소 검색의 구현이 가능하다. 기가비트 라우터의 IP 주소 검색은 최장 프로픽스일치 기법을 사용하여 라우팅 엔트리를 검색하는데, 56Gbps 속도를 지원하기위해서는 평균 513byte의 패킷을 800 nsec 이하의 속도로 처리하여야 한다. 본 논문에서는 범용 펜티엄 프로세서의 캐쉬 크기에 적합한 고속 라우팅을 위한 포워딩 테이블 구조를 제안하였으며, 400 MHz의 페티엄 II 프로세서를 이용한 실험에서 초당 수백만개의 IP 주소 검색을 실현하였다. 제안된 포워딩 테이블은 약 48,000여개의 실제 라우팅 엔트리에 대해 284Kbyte의 매우 작은 크기로 작성되었는데, 이 크기는 펜티엄 프로세서의 L2 케쉬에 저장될 수 있는 작은 크기이다. 제안된 포워딩 테이블을 이용한 평균 검색 시간은 라우팅 테이블 별로 320~530 nsec가 소요되었다.