• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.172-178
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• 1986

The recent interest in the design of filters is motivatied by the fact that such filter can be fully integrated using standard metal-oxide-semiconductor processing technology. This is due to replacing all the resistors in the active RC filter network by the switched capacitors. The voltage gain of a SC filter depends only on the rations of capacitance and these ratios can be obtained and maintained to high accuracy. Therefore, it is known that a switched capacitor is much better than a resistor in temperature and linearity characteristics. This paper proposed a programmable SC filter and proved the fact that ${omega}_0$ Q and G of this circuit can be controlled by digital signal. Experiments show that SC filter remains the low sensitivities but it can't avoid little influence of parasitic capacitance. As the transfer characteristic of the SC filter is varied with sampling frequency and resistor array, SC filtering technigue can be applied for digital processing, speech analysis and synthesis and so on.

• Korean Journal of Optics and Photonics
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• v.24 no.1
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• pp.1-8
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• 2013

In this paper, we report design, fabrication and characterization of the WBRM (Wide Band Receiver Module) for LADAR (LAser Detection And Ranging) application. The WBRM has been designed and fabricated using self-made APD (Avalanche Photodiode) and TIA (Trans-impedance Amplifier). The APD and TIA chips have been integrated on 12-pin TO8 header using self-made ceramic submount and circuit. The WBRM module showed 450 ps of rise time, and corresponding 780 MHz bandwidth. Furthermore, it showed very low output noise less than 0.8 mV, and higher SNR than 15 for 150 nW of MDS(Minimum Detectable Signal). To the author's knowledge, this is the best performance of an optical receiver module for LIDAR fabricated by 200 um InGaAs APD.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.