• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.9
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• pp.785-795
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• 1990

For the far field radiation pattern of a microstrip array antenna which is conformed to a cylindrical surface and forms an arc array, an approximate analysis method using FOURIER TRANSFORM is presented. In this method, the conformal array antenna is projected on the effective aperture plane and assumed to be an aperiodic array with nonlinear phase tilt. The effective aperture plane includes four end-points of each arc on the cylindrical surface. When the effective aperture ratio which is normalized to the planar type is from 1.0 to 0.9, it is confirmed that this approximate method is valid. To the array on the effective aperture plane, it is assumed that the phase tilt is due to the distance between aperture plne and curvature surface. Specially, when the radius of arc is more than 5 times to its length, the FOURIER TRANSFORM METHOD could be used with only varying scale factors. The results of calculating by approximate method are good agreement with the results of COORDINATE TRANSFORM METHOD and experimentally measured value in the range of -40dB. And, the difference of half power angle is less than 5 degrees when the effective aperture ratio moer than 0.9.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.342-349
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• 2008

This paper presents a new digit-serial systolic multiplier over $CF(2^m)$ for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every ${\lceil}m/D{\rceil}$ clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.

• The Bulletin of The Korean Astronomical Society
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• v.43 no.1
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• pp.49.3-49.3
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• 2018

가시광 CCD나 HxRG 등의 적외선 어레이 디텍터는 천문관측기기를 구성하는 핵심부품으로, 관측기기의 종합 성능 결정에 중요한 영향을 미친다. 따라서 디텍터의 성능을 정확하게 진단하는 것은 관측기기의 성능을 예측하거나 유지 또는 개선하는데 중요한 요소가 된다. 한국천문연구원은 최근에 디텍터 성능을 직접적으로 측정할 수 있는 광전자 시스템을 구축하고 장치를 구동하기 위한 소프트웨어를 자체 개발하였다. 본 시스템을 기반으로 Andor iKon-M 카메라 CCD의 시스템 게인, 최대 포화전자수, 감도, 비선형성, 양자효율, 암전류, 읽기 잡음, 불량 픽셀의 특성을 측정하였으며 특히, 양자효율의 경우 디텍터의 구동 온도에 따라 파장별로 2%에서 30% 이상까지 편차가 발생하는 것을 확인하였다. 본 연구는 디텍터의 성능 평가와 그 중요성에 대하여 논의한다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.24-26
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• 2000

본 논문에서는 RSA 암호 시스템의 핵심 과정인 모듈로 멱승(Modular Exponentiation) 연산에 대한 새로운 하드웨어 구조를 제시한다. 기존의 몽고메리 알고리즘을 사용하였지만 다른 논문들이 Dependence Graph를 수직으로 매핑(Mapping)한 것과는 달리 여기서는 수평으로 매핑하여 1차원 선형 어레이(linear array) 구조를 구성하였다. 본 논문에서 사용한 방법의 장점은 결과가 시리얼(serial)로 나와서 바로 입력으로 들어갈 수 있기 때문에 100%의 처리율(throughput)을 이룰 수 있고, 수직 매핑 방식에 비해 절반의 클럭 횟수로 연산을 해낼 수 있다는 점이다. 또한 내부 계산 구조의 지역성(Locality) , 규칙성(Regularity) 및 모듈성(Modularity) 등으로 인해 실시간 고속 처리를 위한 VLSI 구현에 적합하다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.149-150
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• 2015

압전 마이크로머신 초음파 트랜스듀서(Piezoelectric micro-machined ultrasonic transducers)는 DC 바이어스 전압을 인가해야 구동되는 특성을 가지고 있다. 따라서 초음파 트랜스 듀서를 구동하기 위한 전력증폭기는 DC 바이어스 전압이 요구되므로 기존의 전력증폭기에 비해 효율이 매우 낮아지게 된다. 이를 해결하기 위해 본 논문에서는 압전 마이크로머신 초음파 트랜스듀서를 구동하기 위한 고효율 전력증폭기를 제안한다. 전력증폭기는 AMP부와 전원부로 나뉘며, AMP부는 Class B Amp를 사용하여 높은 증폭 선형성을 갖는다. 전원부는 Amp를 구동하기위한 DC-DC converter가 에너지 회수 동작을 하므로 전력증폭기의 효율을 높일 수 있다. 본 연구에서는 압전 마이크로머신 초음파 트랜스듀서를 구동하기 위한 전력증폭기 회로를 제시하고 시뮬레이션과 실험을 통해 동작 특성을 검증한다.

• Journal of Biomedical Engineering Research
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• v.25 no.5
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• pp.391-401
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• 2004

3D imaging systems using 2D phased arrays have a large number of active channels, compelling to use a very expensive and bulky beamforming hardware, and suffer from low volume rate because, in principle, at least one ultrasound transmit-receive event is necessary to construct each scanline. A high speed 3D imaging method using a cross array proposed previously to solve the above limitations can implement fast scanning and dynamic focusing in the lateral direction but suffer from low resolution except at the fixed transmit focusing along the elevational direction. To overcome these limitations, we propose a new real-time volumetric imaging method using a cross array based on the synthetic aperture technique. In the proposed method, ultrasound wave is transmitted successively using each elements of an 1D transmit array transducer, one at a time, which is placed along the elevational direction and for each firing, the returning pulse echoes are received using all elements of an 1D receive array transducer placed along the lateral direction. On receive, by employing the conventional dynamic focusing and synthetic aperture method along lateral and elevational directions, respectively, ultrasound waves can be focused effectively at all imaging points. In addition, in the proposed method, a volume of interest consisting of any required number of slice images, can be constructed with the same number of transmit-receive steps as the total number of transmit array elements. Computer simulation results show that the proposed method can provide the same and greatly improved resolutions in the lateral and elevational directions, respectively, compared with the 3D imaging method using a cross array based on the conventional fixed focusing. In the accompanying paper, we will also propose a new real-time 3D imaging method using a cross array for improving transmit power and elevational spatial resolution, which uses linear wave fronts on transmit.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.6
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• pp.301-309
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• 2001

본 논문에서는 RSA 암호 시스템의 핵심 과정인 모듈로 멱승 연산에 대한 새로운 하드웨어 구조를 제시한다. 본 방식은 몽고메리 곱셈 알고리즘을 사용하였으며 기존의 방법들이 데이터 종속 그래프(DG : Dependence Graph)를 수직으로 매핑한 것과는 달리 여기서는 수평으로 매핑하여 1차원 선형 어레이구조를 구성하였다. 그 결과로 멱승시에 중간 결과값이 순차적으로 나와서 바로 다음 곱셈을 위한 입력으로 들어갈 수 있기 때문에 100%의 처리율(throughput)을 이룰 수 있고, 수직 매핑 방식에 비해 절반의 클럭 횟수로 연산을 해낼 수 있으며 컨트롤 또한 단순해지는 장점을 가진다. 각 PE(Processing Element)는 2개의 전가산기와 3개의 멀티플렉서로 이루어져 있고, 암호키의 비트수를 k비트라 할 때 k+3개의 PE만으로 파이프라인구조를 구현하였다. 1024비트 RSA데이터의 암호 똔느 복호를 완료하는데 2k$^2$+12k+19의 클럭 수가 소요되며 클럭 주파수 100Mhz에서 약 50kbps의 성능을 보인다. 또한, 제안된 하드웨어는 내부 계산 구조의 지역성(locality), 규칙성(regularity) 및 모듈성(modularity) 등으로 인해 실시간 고속 처리를 위한 VLSI 구현에 적합하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1322-1328
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• 1999

In this paper, we propose a Multiple Signal Classification(MUSIC) in conjunction with signal enhancement (SE-MUSIC) for solving the direction-of-arrival estimation problem of multiple incoherent plane waves incident on a uniform linear array. The proposed SE-MUSIC algorithms involve the following main two-step procedure : ( i )to find the enhanced matrix that possesses the prescribed properties and which lies closest to a given covariance matrix estimate in the Frobenius norm sense and (ii) to apply the MUSIC to the enhanced matrix. Simulation results are illustrated to demonstrate the better resolution and statistical performance of the proposed method than MUSIC at lower SNR.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.161-166
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• 2008

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF($2^m$) using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.5
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• pp.535-539
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• 2010

We present a digital dilution chip comprising a $2{\times}6$ array of wells; the chip can be employed to change the dilution ratio as well as to initiate reactions among diluted samples by using the inter-well valve around the well. In previous dilution devices, streams comprising sample and dilution solutions were merged and separated by a branched microchannel. Therefore, the dilution ratio could not be changed until the structure of the branched microchannel was changed. The present device merges and splits the wells filled with sample or dilution solution by controlling inter-well valves around the wells. Thus, it is possible to change the dilution ratio by changing the sequence in which merging and splitting sequence of each well filled with sample or dilution solution. In experiments, we found that the chip could be used to change linear or exponential dilution ratios within an error of 16.7% and to initiate reactions among the samples within a reaction error of 17.7%.