• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.507-511
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• 2018

This paper proposes a method for system development for high speed (300MHz) test of system IC semiconductors. The high-speed test system proposes a high-speed test circuit interface and a PCB design method for noise reduction. This paper proposes evaluation items and procedures for verifying the performance of the developed system. System IC The development of high speed test systems will help optimize the development of domestic system IC test equipment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.747-749
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• 2012

This paper is analyzing the SoC policy of major nations as the U.S, Japan, Europe, Taiwan, China and draw the suggestions for the development of semiconductor industry in Korea. SoC is the non-memory semiconductor to support and put into action the function of system. SoC is big market over the 200billion dollars and have a huge potential for new IT convergence market. Developed countries as the US, Japan, and Europe have enforced the industrial competitiveness by company investment and Taiwan supported the SoC Industry by government fund. Korea is No.1 superpower in DRAM semiconductor, but very weak in SoC Industry. We should secure the competitiveness of SoC Industry by the development of core technology, planning the growth policy, and building the cooperative model to leap the SoC power nation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.845-848
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• 2009

Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronics circuits. Theyare also caleed power devices or when used in integrated circuits, called power ICs. Some common power devices are the power diode, thyristor, power MOSFET and IGBT (insulated gate bipolar transistor). A power diode or MOSFET operates on similar principles to its low-power counterpart, but is able to carry a larger amount of current and typically is able to support a larger reverse-bias voltage in the off-state. Structural changes are often made in power devices to accommodate the higher current density, higher power dissipation and/or higher reverse breakdown voltage. The vast majority of the discrete (i.e non integrated) power devices are built using a vertical structure, whereas small-signal devices employ a lateral structure. With the vertical structure, the current rating of the device is proportional to its area, and the voltage blocking capability is achieved in the height of the die. With this structure, one of the connections of the device is located on the bottom of the semiconductor.

• Korean Management Science Review
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• v.18 no.1
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• pp.1-13
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• 2001

Despite that the semiconductor industry plays an important role to our economy, it has abnormal industrial structure stressing too much on memory chips. Thus, it is essential for our corporate to develop nonmemory chips to obtain technological leadership in a highly competitive semiconductor market. In this study, we demonstrate how benefit/cost analysis using the Analytic Hierarchy process (AHP) can be used for the proper selection of nonmemory semiconductor chips: Microprocessor, ASIC, digital IC and Analogue IC. The final results show that ASIC is the most attractive chip to develop, followed by Analogue IC, digital IC and Microprocessor. This is Somewhat consistent with the information that we found with respect to the elements that were taken into consideration. Sensitivity analysis is also provided here.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.353-356
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• 2001

기존의 범용시스템과 대별되는 임베디드 시스템의 수요가 급증하면서 하드웨어부분의 중심축인 임베디드 프로세서에 대한 관심이 하루가 다르게 커지고 있다. 또한 사용자들이 작고 간편하면서도 기존의 범용시스템과 같은 기능들을 가지는 높은 수준의 성능을 요구하게 됨으로서 한 칩 안에 여러 가지 기능을 함께 구현하거나 시스템을 집적하는 시스템 칩의 상품화가 이루어지고 있는 추세이다. 날로 경쟁이 치열해저 가는 비메모리 설계 분야에서 누가 더욱 우수한 반도체 관련 IP를 확보하느냐가 승패의 관건이 될 것은 당연한 일이 되었다. 된 논문에서는 기존에 성능이 검증된 SPARC 아키텍처 V8을 근간으로 한 VHDL모델을 분석하고, 시뮬레이션을 통하여 그 기능을 검증하였으며, Synopsys FC2(FPGA Compiler 2)를 이용하여 로직 합성하였으며, 그 결과를 Xilinx VIRTEX 3000 FPGA를 이용하여 구현하였다.

• Journal of Advanced Navigation Technology
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• v.17 no.5
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• pp.560-567
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• 2013

In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.41-47
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• 2020

The effect of Co interlayer on the interfacial reliability of SiN_x/Co/Cu thin film structure for advanced Cu interconnects was systematically evaluated by using a double cantilever beam test. The interfacial adhesion energy of the SiN_x/Cu thin film structure was 0.90 J/㎡. This value of the SiN_x/Co/Cu thin film structure increased to 9.59 J/㎡.Measured interfacial adhesion energy of SiN_x/Co/Cu structure was around 10 times higher than SiN_x/Cu structure due to CoSi₂ reaction layer formation at SiN_x/Co interface, which was confirmed by X-ray photoelectron spectroscopy analysis. The interfacial adhesion energy of SiN_x/Co/Cu structure decreased sharply after post-annealing at 200℃ for 24 h due to Co oxidation at SiN_x/Co interface. Therefore, it is required to control the CoO and Co₃O₄ formation during the environmental storage of the SiN_x/Co/Cu thin film to achieve interfacial reliability for advanced Cu interconnections.