• Journal of KIISE:Computer Systems and Theory
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• v.29 no.1
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• pp.42-56
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• 2002

It is possible but not efficient to model and simulate asynchronous microprocessors with the existing HDLs(HARDware Description Languages) such as VHDL or Verilog. The reason it that the description becomes too complex. and also the simulation time becomes too long to explore the design space. Therefore it is necessary to establish a methodology and develop a tool for modeling the handshake protocol of asynchronous microprocessors very easily and simulating it very fast. Under this objective an efficient CAD(Computer Aided Design) tool SLEDS(System Level Event-Driven Simulator) was developed which can evaluate performance of a processor through modeling with a simple description an simulating with event driven engine in the system level. The ultimate goal in the tool SLEDS is to fin the optimal conditions for a system to produce high performance by balancing the delay of each module in the system. Besides SLEDS aims at verifying the design through comparing the expected results with the actual ones by performing the defined behavior.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.06a
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• pp.1152-1155
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• 1998

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.1976-1979
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.10a
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• pp.447-452
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• 2004

동기전동기를 처음 기동시킬 때는 유도전동기와 같이 동작하게 된다. 회전자가 고정자 자계에 거의 도달하였을 때 M 전류를 투입하게 되면, 회전자의 여자코일에 동기화 토크가 발생하게 된다. 그러나 동기화 토크의 부족은 회전자의 첫 동요 시, 회전자 각의 불안정을 야기하게 된다. 동기화 토크는 신속 정확한 동작 제어에 의해 회복될 수 있다. 더욱이 역률 100%의 안정도로 동작하기에는 어려운 부분이 있다. 그러므로 본 논문에서는 이러한 문제를 해결하기 위해 퍼지 추론 기법을 이용한 여자 전류 제어 시스템을 제안하였다. 그 주된 원리는 다양한 부하 조건하에서 부하각과 역률 100%의 동작점을 추정하고, 퍼지 추론 기법에 의해 여자 전류를 제어하는 것이다. 제안된 퍼지 제어기는 각종 특수 동작 명령어로 사용되는 마이크로프로세서형 PLC(Programmable Logic Controller)를 사용하여 구현되었으며, 전기자 전류를 감지하는 제어전압 보상기, 비교기, 그리고 쵸퍼회로로 구성된 기존의 제어기에 비해 성능이 우수하다. 이는 일련의 실험을 통해 역률 100%에서의 개선된 안정적인 동작이 가능함을 보여주었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1224-1226
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• 2007

전압형 인버터에 의해 제어되며 인버터의 스위칭 게이트 신호 발생은 전압변조가 필요하다. 전압변조는 삼각파 비교 PWM, 공간전압벡터(Space voltage Vector) PWM기법 등으로 실현되고 있으나, SVPWM은 타 방식에 비해 고조파의 왜형률을 감소시키고, 디지털 구현이 용이하며 선형제어 영역을 증가시킬 수 있는 장점이 있다. 따라서 본 논문에서는 먼저 SVPWM의 스위칭 이론 및 각 섹터에 따른 방향에 대해 설명하였고, 태양광발전 시스템을 3상 PWM전압형 인버터로 구성하였고 안정된 변조를 위해서 동기신호와 제어신호를 위해 모토로라사의 56F8323 마이크로프로세서에 의해서 처리하였다. 또한 시스템의 출력전압과 전류의 파형은 전원전압과 출력전류가 위상이 일치되어 단위 역률로 안정된 전력을 공급할 수 있도록 제어하였다.

• Journal of the Korea Society of Computer and Information
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• v.14 no.2
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• pp.157-168
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• 2009

In this paper, a photovoltaic system is designed with a step up chopper and single phase PWM(Pulse Width Modulation) voltage source inverter. Where proposed Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper operates in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature because solar cell has typical voltage and current dropping character. The single phase PWM voltage source the inverter using inverter consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be developed continuously by connecting with the source of electric power for ordinary use. It can cause the effect of saving electric power. from 10 to 20[%]. The single phase PWM voltage source inverter operates in situation that its output voltage is in same phase with the utility voltage. In order to enhance the efficiency of photovoltaic cells, photovoltaic positioning system using sensor and microprocessor was design so that the fixed type of photovoltaic cells and photovoltaic positioning system were compared. In result, photovoltaic positioning system can improved 5% than fixed type of photovoltaic cells. In addition, I connected extra power to the system through operating the system voltage and inverter power in a synchronized way by extracting the system voltage so that the phase of the system and the phase of single-phase inverter of PWM voltage type can be synchronized. And, It controlled in order to provide stable pier to the load and the system through maintaining high lurer factor and low output power of harmonics.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.3
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• pp.110-115
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• 2002

This paper proposes the adaptive fuzzy control system using the microprocessesor for high precision control of automation systems which exist non-linearities such as saturation, relays, hysteresis, and dead zones. The proposed system which provides the improvement in terms of the control region in transient and adaptive control, first used the frequence-locked mothed driving a system to generate a output voltage proportional to the frequency diffierence of relnence input signal and feedback signal for fast transient response,, and when the error reaches the preset value, used the adaptive fuzzy logic for precision control. The theoretical and experimental studies have been carried out. The presented results from the above investigation show considerable improved performance in the precision control of servo control systems.