• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.59-65
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• 2001

3GPP proposed a variant CBC-MAC based on the block cipher KASUMI to provide the data integrity over a radio access link. We have studied deeply the Knudsen and Mitchell\`s attack. In this paper we proposed a definite performing algorithm of the Knudsen and Mitchell\`s alack and compute the success probability and complexity of that algorithm. Moreover We also analyze a security of 3GPP-MAC comparing with the original CBC-MAC.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.103-108
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• 2016

With the growing trend of pervasive computing, (the idea that technology is moving beyond personal computers to everyday devices) there is a growing demand for lightweight ciphers to safeguard data in a network that is always available. For all block cipher applications, the AES is the preferred choice. However, devices used in pervasive computing have extremely constraint environment and as such the AES will not be suitable. In this paper we design and implement a new lightweight compact block cipher that takes advantage of both S-P network and the Feistel structure. The cipher uses the S-box of PRESENT algorithm and a key dependent one stage omega permutation network is used as the cipher's P-box. The cipher is implemented on iNEXT-V6 board equipped with virtex-6 FPGA. The design synthesized to 196 slices at 337 MHz maximum clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.495-504
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• 2012

This paper presents various speed optimization techniques for software implementation of the HIGHT block cipher on CPUs and GPUs. We considered 32-bit and 64-bit operating systems for CPU implementations. After we applied the bit-slicing and byte-slicing techniques to HIGHT, the encryption speed recorded 1.48Gbps over the intel core i7 920 CPU with a 64-bit operating system, which is up to 2.4 times faster than the previous implementation. We also implemented HIGHT on an NVIDIA GPU equipped with CUDA, and applied various optimization techniques, such as storing most frequently used data like subkeys and the F lookup table in the shared memory; and using coalesced access when reading data from the global memory. To our knowledge, this is the first result that implements and optimizes HIGHT on a GPU. We verified that the byte-slicing technique guarantees a speed-up of more than 20%, resulting a speed which is 31 times faster than that on a CPU.

• Journal of the Korea Society of Computer and Information
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• v.27 no.12
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• pp.171-178
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• 2022

In this paper, we propose a classification method according to the type and characteristics of stablecoins for risk analysis, and analyze the risk factors of each stablecoin based on this classification. First, this paper explains the technologies and ecosystem of blockchain and decentralized finance(DeFi) to understand stablecoins. In addition, the operation principle of the major stablecoins currently released and used is explained for each proposed classification type. Based on this, the risk type and risk factors of each stablecoin are derived. The risk types proposed in this paper are classified as defegging, liquidation, and exploit, and the risk factors are classified as depegging due to reliability of operator, depegging due to reliability of algorithm, depegging due to failure of algorithm, liquidation due to high volatilty and oracle attack. Based on the proposed classification, we analyze the risk factors of major stablecoins currently circulating in the crypto market.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.4
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• pp.569-575
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• 2024

The 64-bit block cipher IIoTBC is an encryption algorithm designed for the security of industrial IoT devices and uses an 128-bit secret key. The IIoTBC's encryption algorithm varies depending on whether the MCU size used in IoT is 8-bit or 16-bit. This paper deals with a differential attack on IIoTBC when the MCU size is 8-bit. It attacks 15-round out of the entire 32-round using IIoTBC's 14-round differential characteristic. At this time, the number of required plaintexts and encryption are 2⁵⁷ and 2^122.4, respectively. The differential characteristic presented in this paper has a longer round than the existing 13-round impossible differential characteristic, and the attack using this is the result of the first key recovery attack on IIoTBC.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1225-1236
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• 2020

Fuzzing is an automated software testing methodology that dynamically tests the security of software by inputting randomly generated input values outside of the expected range. KISA is releasing open source for standard cryptographic algorithms, and many crypto module developers are developing crypto modules using this source code. If there is a vulnerability in the open source code, the cryptographic library referring to it has a potential vulnerability, which may lead to a security accident that causes enormous losses in the future. Therefore, in this study, an appropriate security policy was established to verify the safety of block cipher source codes such as SEED, HIGHT, and ARIA, and the safety was verified using differential fuzzing. Finally, a total of 45 vulnerabilities were found in the memory bug items and error handling items, and a vulnerability improvement plan to solve them is proposed.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.153-158
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• 2006

P. Kocher에 의해 DPA 공격이 소개된 이후 이를 방어하기 위한 연구가 활발하게 진행되고있다. 그에 대한 일환으로 블록암호알고리즘 구현 시 소프트웨어적인 대응방안으로 마스킹 기반의 대응기법이 많이 사용되고 있으며 이는 1차 DPA 공격에 안전한 것으로 인지되어 왔다. 본 논문에서는 부주의하게 구현된 마스킹 기반의 대응기법이 2차 DPA 공격이 아닌 1차 DPA 공격에도 취약한 사실을 증명하였으며 이를 실험을 통해서 검증하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.587-589
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• 2000

이 논문은 한국정보통신기술협회에 의해 1998년 11월에 제정된 HAS-160 해쉬 함수를 하드웨어로 구현하였다. SET(Secure Electronic Transaction) 혹은 SSL(Secure Socket Layer)등의 암호 프로토콜에서 하나의 구성 요소를 이루기 위해 설계되었고 초기값을 원래의 알고리즘에서 주어진 값이 아닌 사용자 혹은 프로토콜이 요구하는 값으로 입력할 수 있게 하였다. 전체적으로 회로는 VHDL top-down 설계 방법을 따랐고 IEEE 표준 라이브러리만을 사용하여 범용성을 가진다. 그리고 블록들은 내부적으로 행위적 수준(behavior level)에서 설계되었고 설계된 각각의 블록들은 구조적 수준(structure-level)에서 연결되었다. 설계된 회로는 125MHz의 클럭 주파수와 26Mbps의 성능으로 동작하며 ALTERA FLEX10K EPF10K200칩에서 6018(60%)개의 셀을 차지한다.