• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.808-810
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• 2005

조건 분기예측실패는 많은 사이클을 낭비시키며, 비순서적 실행을 방해하고, 잘못 예측된 명령어들을 수행하게 되므로 전력을 낭비한다. gshare와 GAg같은 전역 히스토리를 기반으로 하는 예측기에서는 히스토리의 명령어 완료시간 갱신(commit update)에 의해 많은 분기예측실패가 발생한다. 이를 위해 히스토리를 모험적으로 갱신하고, 분기예측실패 시 히스토리를 복구시키는 메커니즘에 관한 연구들이 제시되었다. 본 논문에서는 기존 분기예측기에 age_Counter를 추가하여 미해결 분기명령어 수를 저장하며, 이를 분기예측실패 후 분기 히스토리 레지스터를 복구하는데 사용하는 간단한 복구 메커니즘을 제안한다. SimpleScalar 3.0/PISA 툴셋과 SPECINT95 벤치마크 프로그램에서 시뮬레이션 한 결과, 제안된 복구 메커니즘은 GAg와 gshare 예측기에서 예측정확도는 각각 $9.21\%$와 $2.14\%$가 개선되었고, IPC는 $18.08\%$와 $8.75\%$ 개선되었다.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.306-313
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• 2005

Conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a simple mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the Simplescalar 3.0/PISA tool set and the SPECINTgS benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14$\%$ and 9.21$\%$, respectively and the average IPC by 8.75$\%$ and 18.08$\%$, respectively over the original predictor.

• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.217-226
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• 2008

Branch prediction accuracy is critical for system performance in modern microprocessor architectures. The use of speculative update branch history provides substantial accuracy improvement in branch prediction. However, speculative update branch history is the information about uncommitted branch instruction and thus it may hurts program correctness, in case of miss-speculative execution. Therefore, speculative update branch history requires suitable recovery mechanisms to provide program correctness as well as performance improvement. In this paper, we propose recovery logics for speculative update branch history. The proposed solutions are recovery logics for both global history and local history. In simulation results, our solution provides performance improvement up to 5.64%. In addition, it guarantees the program correctness and almost 90% of additional hardware overhead is reduced, compared to previous works.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.19-30
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• 2008

Branch history is one of major input vectors in branch prediction. Therefore, the Proper use of branch history plays a critical role of improving branch prediction accuracy. To improve branch prediction accuracy, this paper proposes a new branch history management policy, based on interrelationship analysis of instructions. First of all, we propose three different algorithms to analyze the relationship: register-writhing method, branch-reading method, and merged method. Then we additionally propose variable input gshare predictor as an implementation of these algorithms. In simulation part, we provide performance differences among the algorithms and analyze their characteristics. In addition, we compare branch prediction accuracy between our proposals and conventional fixed input predictors. The performance comparison for optimal input branch predictor is also provided.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.33-40
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• 2007

Processor pipelines have been growing deeper and issue widths wider over the years. If this trend continues, the branch misprediction penalty will become very high. Branch misprediction is the single most significant performance limiter for improving processor performance using deeper pipelining. Therefore, more accurate branch predictor becomes an essential part of modern processors. Several branch predictors combine a part of the branch address with a fixed amount of global branch history to make a prediction. These predictors cannot perform uniformly well across all programs because the best amount of branch history to be used depends on the program and branches in the program. Therefore, predictors that use a fixed history length are unable to perform up to their potential performance. In this paper, we propose a branch prediction mechanism, using variable length history, which predicts using a bank having higher prediction accuracy among predictions from five banks. Bank 0 is a bimodal predictor which is indexed with the 12 least significant bits of the branch address. Banks 1, 2, 3 and 4 are predictors which are indexed with different global history bits and the branch PC. In simulation results, the proposed mechanism outperforms gshare predictors using fixed history length of 12 and 13 , up to 6.34% in prediction accuracy. Furthermore, the proposed mechanism outperforms gshare predictors using best history lengths for benchmarks, up to 2.3% in prediction accuracy.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.22-24
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• 2001

슈퍼스칼라 프로세서에서는 분기 명령의 결과 지연으로 명령의 공급이 중단되는 것을 방지하고 지속적인 파이프라인 처리를 위해서 분기의 결과를 미리 예측하여 명령을 폐치하고 있다. 본 논문에서는 심플스칼라 툴 셋을 사용하여 슈퍼스칼라 프로세서에서 사용되는 대표적인 동적 분기예측 방법 시뮬레이션 환경을 구축한다. 동적 분기예측 방법으로 분기 타겟버퍼(Branch Target Buffer, BTB) 상에서 분기명령의 자기 히스토리에 근거한 BTB 방식과 이전 분기명령의 히스토리와의 상관관계를 고려한 Gshare 분기예측기를 적용 구현한다. 심플스칼라 시뮬레이터에 SPEC95 벤치마크 프로그램을 실행시켜 디자인 파라미터 변화에 따른 분기 예측기의 예측정확도를 실험한다. 또한 BTB와 Gshare 분기예측기를 VHDL로 구현하고 Synopsys 툴을 이용하여 시뮬레이션 및 합성 과정을 거쳐 게이트 크기와 파워 소모량을 측정한다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.2 s.314
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• pp.1-10
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• 2007

Branch prediction accuracy is critical for the overall system performance. Branch miss-prediction penalty is the one of the significant performance limiters for improving processor performance, as the pipeline deepens and the instruction issued per cycle increases. In this paper, we propose "Dynamic Per-Branch History Length Fitting Method" by tracking the data dependencies among the register writing instructions. The proposed solution first identifies the key branches, and then it selectively uses the histories of the key branches. To support this mechanism, we provide a history length adjustment algorithm and a required hardware module. As the result of simulation, the proposed mechanism outperforms the previous fixed static method, up to 5.96% in prediction accuracy. Furthermore, our method introduces the performance improvement, compared to the profiled results which are generally considered as the optimal ones.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.766-768
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• 2005

분기 영령어의 예측 정확도는 시스템 전체 성능에 중대한 영향을 미친다. 여러 분기 예측 방식 가운데 하나인 "분기 정보의 투기적 사용" 은 분기 명령어의 가장 최근 기록을 일관되게 사용할 수 있도록 도와줌으로 해서 분기 예측의 정확도 향상에 크게 기여한다. 하지만 이와 같은 기법은 미완료 분기에 대한 히스토리를 투기적으로 사용하는 방식이다. 따라서 사용되는 정보가 올바르지 못할 수 있으며, 이런 경우 적절한 복구 기법을 필요로 한다. 본 논문에서는 분기 정보의 투기적 사용에 대한 필요성과 효율적인 복구 기법을 제안한다. 제안된 기법은 이전 연구와 비교하여 상당한 하드웨어 요구량의 감소를 가져왔으며, 또한 프로그램 수행의 정확성을 해치지 않으면서 최대 $3.3\%$의 성능향상을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.10-17
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• 2013

This thesis proposes an automatic embedded core generator system that supports branch prediction. The proposed system includes a dynamic branch prediction module that enhances execution speed of target applications by inserting history/direction flags into BTAC(Branch Target Address Cache). Entries of BHT(Branch History Table) and BTAC are determined based on branch informations extracted by simulation. To verify the effectiveness of the proposed branch prediction module, ARM9TDMI core including a dynamic branch predictor was described in SMDL and generated. Experimental results show that as the number of entry rises, area increase up to 60% while application execution cycle and BTAC miss rate drop by an average of 1.7% and 9.6%, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.1
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• pp.117-122
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• 2023

This paper introduces the improved and expanded contents of the previous research that implemented a system that guides the visually impaired using the vibration of a smart watch. In the previous study, we proposed an algorithm that recommends the most safe route based on calculating negative and positive values for the topography of the route and the features installed on the route. In addition, by designing several vibration patterns, a system that guides the user through vibration was proposed and implemented. In this paper, the user's personal preferences are reflected in the algorithm that recommends the safe route first. In addition, an automatic feedback function was added to the algorithm so that the user's satisfaction evaluation on the recommended route was immediately reflected. A history simulation function was added so that the past route could be reviewed, and the compass of a smart watch was used to help visually impaired people find directions at junctions.