• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.1-14
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• 2006

The indirect branch instruction is a most substantial obstacle in utilizing ILP of modem high performance processors. The target address of an indirect branch has the polymorphic characteristic varied dynamically, so it is very difficult to predict the accurate target address. Therefore the performance of a processor with speculative methodology is reduced significantly due to the many execution cycle delays in occurring the misprediction. We proposed the very accurate and novel indirect branch prediction scheme so called data-dependence based prediction. The predictor results in the prediction accuracy of 98.92% using 1K entries, and. 99.95% using 8K But, all of the proposed indirect predictor including our predictor has a large hardware overhead for restoring expected target addresses as well as tags for alleviating an aliasing. Hence, we propose the scheme minimizing the hardware overhead without sacrificing the prediction accuracy. Our experiment results show that the hardware is reduced about 60% without the performance loss, and about 80% sacrificing only the performance loss of 0.1% in aspect of the tag overhead. Also, in aspect of the overhead of storing target addresses, it can save the hardware about 35% without the performance loss, and about 45% sacrificing only the performance loss of 1.11%.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.181-190
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• 1996

Pipelined architecture improves processor performance by overlapping the execution of several different instructions. The effect of control hazard stalls the pipeline and reduces processor performance. In order to reduce the effect of control hazard caused by branch, we proposes a new approach combining both branch prediction and two paths strategy. In addition, we verify the performance improvement in a proposed approach by utilizing system performance metric CPI rather than BEP.

• Journal of Korean Society of Transportation
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• v.32 no.6
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• pp.600-614
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• 2014

This paper develops a model to forecast container volumes of all Korean seaports using a Seasonal ARIMA (Autoregressive Integrated Moving Average) technique with the quarterly data from the year of 1994 to 2010. In order to verify forecasting accuracy of the SARIMA model, this paper compares the predicted volumes resulted from the SARIMA model with the actual volumes. Also, the forecasted volumes of the SARIMA model is compared to those of an ARIMA model to demonstrate the superiority as a forecasting model. The results showed the SARIMA Model has a high level of forecasting accuracy and is superior to the ARIMA model in terms of estimation accuracy. Most of the previous research regarding the container-volume forecasting of seaports have been focussed on long-term forecasting with mainly monthly and yearly volume data. Therefore, this paper suggests a new methodology that forecasts shot-term demand with quarterly container volumes and demonstrates the superiority of the SARIMA model as a forecasting methodology.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.9-11
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• 2000

최근에 캐쉬의 성능이 전체 시스템에 미치는 영향이 커짐에 따라 캐쉬의 성능을 모델링하고 향상시키기 위한 많은 연구가 진행되고 있다. 본 논문에서는 네 가지 종류의 캐쉬모델을 가정하고 분기명령어 비율, 캐쉬미스율, 분기예측 실패율 등의 파라메터를 이용하여 수퍼스칼라 프로세서에서의 명령어 패치율을 해석적으로 모델링하였다. 시뮬레이션 결과 분기예측실패가 명령어 패치율에 미치는 영향보다는 캐쉬미스율이나 캐쉬미스 패널티의 증가로 인한 패치율의 감소가 더욱 큰 폭으로 나타났다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1939-1947
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• 2000

본 논문에서는 명령어의 효율적인 페치를 위해 분기 타겟 주소 전체를 사용하지 않고 캐쉬 메모리(cache memory) 내의 적은 비트 수로 인덱싱 하여 한 클럭 사이클 안에 최대 4개의 명령어를 다음 파이프라인으로 보내줄 수 있는 방법을 제시한다. 본 프리페치 유닛은 크게 나누어 3개의 영역으로 나눌 수 있는데, 분기에 관련하여 미리 부분적으로 명령어를 디코드 하는 프리디코드(predecode) 블록, 타겟 주소(NTA : Next Target Address) 테이블 영역을 추가시킨 명령어 캐쉬(instruction cache) 블록, 전체 유닛을 제어하고 가상 주소를 관리하는 프리페치(prefetch) 블록으로 나누어진다. 사용된 명령어들은 SPARC(Scalable Processor ARChitecture) V9에 기준 하였고 구현은 Verilog-HDL(Hardwave Description Language)을 사용하여 기능 수준으로 기술되고 검증되었다. 구현된 프리페치 유닛은 명령어 흐름에 분기가 존재하더라도 단일 사이클 안에 4개까지의 명령어들을 정확한 예측 하에 다음 파이프라인으로 보내줄 수 있다. 또한 NTA를 사용한 방법은 같은 수의 레지스터 비트를 사용하였을 때 BTB(Branch Target Buffer)를 사용하는 방법과 비교하여 2배정도 많은 개수의 분기 명령 주소를 저장할 수 있는 장점이 있다.

• The Korean Journal of Applied Statistics
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• v.35 no.4
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• pp.517-525
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• 2022

In the era of big data, various data mining techniques have been proposed as major analysis methodologies. As complex and diverse data is mass-produced, data mining techniques have attracted attention as a method that forms the foundation of data science. In this paper, we focused on the decision tree, which is frequently used in practice and easy to understand as one of representative data mining methods. Specifically, we analyzed the effect of the splitting method of decision trees on the model performance. We compared the prediction power and structures of decision tree models with different split methods based on various simulated data. The results show that the linear combination split method can improve the prediction accuracy of decision trees in the case of data simulated from nonlinear models with complex structure.

• International Commerce and Information Review
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• v.16 no.3
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• pp.73-96
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• 2014

The purpose of this research is to evaluate a short-term export demand forecasting model reflecting individual passenger vehicle brands and market characteristics by using Vector Autoregressive (VAR) models that are based on multivariate time-series model. The short-term export demand forecasting model was created by discerning theoretical potential factors that affect the short-term export demand of individual passenger vehicle brands. Quarterly short-term export demand forecasting model for two Korean small vehicle brands (Accent and Avante) were created by using VAR model. Predictive value at t+1 quarter calculated with the forecasting models for each passenger vehicle brand and the actual amount of sales were compared and evaluated by altering subject period by one quarter. As a result, RMSE % of Accent and Avante was 4.3% and 20.0% respectively. They amount to 3.9 days for Accent and 18.4 days for Avante when calculated per daily sales amount. This shows that the short-term export demand forecasting model of this research is highly usable in terms of prediction and consistency.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.3
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• pp.360-365
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• 2003

In this paper, GMDH(Croup Method of Data Handling) algorithm which is proved to be more excellent in efficiency and accuracy of practical use of data is applied to electric power demand forecasting. As a result, it became much easier to make a choice of input data and make an exact prediction based on a lot of data. Also, we considered both economy factors(GDP, export, import, number of employee, number of economically active population and consumption of oil) and climate factors(average temperature) when forecasting. We assumed target forecast period from first quarter 1999 to first quarter 2001, and suggested more accurate forecasting method of electric power demand by using 3-step computer simulation processes(first process for selecting optimum input period, second for analyzing time relation of input data and forecast value, and third for optimizing input data) for improvement of forecast precision. The proposed method can get 0.96 percent of mean error rate at target forecast period.

• Journal of Practical Agriculture & Fisheries Research
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• v.14 no.1
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• pp.3-22
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• 2012

Control independence has been put forward as a significant new source of instruction-level parallelism for superscalar processors. In branch prediction mechanisms, all instructions after a mispredicted branch have to be squashed and then instructions of a correct path have to be re-fetched and re-executed. This paper presents a new branch misprediction recovery mechanism to reduce the number of instructions squashed on a misprediction. Detection of control independent instructions is accomplished with the help of the static method using a profiling and the dynamic method using a control flow of program sequences. We show that the suggested branch misprediction recovery mechanism improves the performance by 2~7% on a 4-issue processor, by 4~15% on an 8-issue processor and by 8~28% on a 16-issue processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.899-902
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• 2005

Pipeline hazard due to branch instructions is the major factor of the degradation on the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the branch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a tag memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single shared tag memory, we can expect the smaller ship size and the faster prediction. This hared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.