• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.55-56
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• 2009

내장형 프로세서에 대한 기능요구사항이 날로 증가함에 따라 데이터 처리량을 늘리기 위한 많은 연구들이 지속되어 왔으며, 그중 파이프라인의 컨트롤 해저드로 인한 성능저하를 최소화하기 위한 분기 예측 기법이 다양한 방식으로 제안되어 왔다. 본 논문에서는 분기예측 방법으로서 구현이 간단하고 분기 예측률이 높은 BTB 방식을 32비트 프로세서에 적용하고, 해당 프로세서를 사용하는 SoC 플랫폼을 구성하여 분기예측기법 사용으로 인한 성능향상을 측정하고, 0.18um ASIC 공정을 적용하여 SoC 플랫폼을 구현한 결과를 제시한다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.1-10
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• 2013

In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.264-276
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• 1995

In this paper, a technique for eliminating conditional branches in the compilers for superscalar processors is presented. The technique consists of three major steps. The first step transforms conditional branches into equivalent expressions using algebraic laws. The second step searches all possible instruction sequences for those expressions using GSO of Granlund/Kenner. Finally an optimal sequence that has the least dynamic count for the target superscalar processor is selected from the GSO output. Experiment result shows that for each conditional branch is the input program matched by one of the optimization patterns, the proposed technique outperforms more than 25% speedup of execution time over the original code when the GNU C compiler and the SuperSPARC processor are used.

• Fire Science and Engineering
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• v.21 no.2 s.66
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• pp.36-41
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• 2007

In this study, we determined TBP(T-branched pipe) would be available in Fire Safety Codes with strength analyses. A common FEM Program(ABAQUS) was used as analyses method, and the analyses results were confirmed by strength tests of the T-branch pipe. As a result, we concluded that the T-branch pipe can be used safely. Further more, we determined what kind of stainless steel pipe can be used in place of carbon steel pipe(KS D 3507). The stainless steel pipe name Is KS D 3576(stainless steel pipe) 10S, so they can be applied for piping in fire protection system.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.25-32
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• 1995

In this paper, we propose to use a parallel-branch subunit model for improved word recognition. The model is obtained by splitting off each subunit branch based on mixture component in continuous hidden Markov model(continuous HMM). According to simulation results, the proposed model yields higher recognition rate than the single-branch subunit model or the parallel-branch subunit model proposed by Rabiner et al[1]. We show that a proper combination of the number of mixture components and the number of branches for each subunit results in increased recognition rate. To study the recognition performance of the proposed algorithms, the speech material used in this work was a vocabulary with 1036 Korean words.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.15 no.3
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• pp.433-440
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• 2002

A branched crack in a semi-infinite plate under uniform tension and bending moment is considered in this study By using the superposition, the stress and moment intensity factors for the branched crack subjected to uniform tension and bending moment we evaluated. The stress intensity factors we obtained by using the finite element method and the J-based mutual integral. The moment intensity factors are calculated by extrapolating the values of the moment new the crack tip. Numerical results lot the normalized stress and moment Intensity factors we shown as functions of the ratio of branched crack length to main crack length and the branching angle.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.3
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• pp.399-409
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• 1998

In this paper, the broad-band design theory for weakly-coupled Tap-Off for CATV systems has been described and the transmission line impedance matching method has been proposed. The fabricated weakly-coupled Tap-Offs based on the above theory and method have been much improved in the frequency characteristics compared with conventional ones. Thus, the useful bandwidth of weakly-coupled Tap-Offs have been extended from 5 to 2000 MHz. It is also recognized that turn numbers of the coils composing the transformer are not integers but 0.9, 1, 1.9, 2, 2.9, etc., in the actual circuits. Further, the practical measurements of the frequency characteristics for a fabricated weakly-coupled Tap-Off show very good agreements with theoretical results, and hence, the validity of the proposed design theory and transmission line impedance matching method have been confirmed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.899-902
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• 2005

Pipeline hazard due to branch instructions is the major factor of the degradation on the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the branch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a tag memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single shared tag memory, we can expect the smaller ship size and the faster prediction. This hared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.297-305
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• 2006

Trace-driven simulation is widely used for measuring the performance of a microprocessor in its initial design phase. However, since it requires much time and disk space, the statistical simulation has been studied as an alternative method. In this paper, statistical simulations are performed for a high performance superscalar microprocessor with a perceptron-based multiple branch predictor. For the verification, various hardware configurations are simulated using SPEC2000 benchmarks programs as input. As a result, we show that the statistical simulation is quite accurate and time saving for the evaluation of microprocessor architectures with multiple branch prediction.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.261-266
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• 2007

내장형 시스템에 보다 강력한 성능이 요구됨에 따라 내장형 마이크로 프로세서는 보다 깊은 파이프라인을 채택하고 있다. 따라서, 내장형 마이크로 프로세서는 보다 정확한 분기 예측기를 필요로 하고 있다. 이러한 상황에서 분기 예특기의 구조, 성능 및 전력 소모와 전체 시스템의 전력 소모 사이의 trade-off를 분석하는 것은 매우 중요하다. 내장형 환경에서 시스템의 전력 소모는 설계 시 매우 중요하게 고려되어야 한다. 특히 내장형 시스템의 요구사항은 동작할 응용 프로그램에 의하여 규정되고, 전력 소모도 응용프로그램의 구조와 강하게 연관되어 있다. 본 논문의 목표는 내장형 환경에서 성능-전력 공간에서 분기 예측기를 분석하는 기법을 제시하는 것에 있다. 이를 통하여, 분기 예측기 테이블의 성능-전력을 고려한 최적화된 크기를 찾을 수 있다. 이러한 목표는 수학적 모델링을 통한 정량적 예측의 수행 및 시뮬레이션 결과와의 비교를 통한 수학적 모델링의 검증의 과정을 통하여 이루어진다. 결과는 우리의 수학적 모델이 성능-전력 공간에서 분기 예측기 테이블의 최적화된 크기 결정의 해법을 제공하고 있음을 보여주고 있다.