• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.805-812
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• 2008

H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.333-340
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• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.1
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• pp.75-78
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• 2008

In this paper, we proposed a novel encoder/decoder for an optical CDMA(code division multiple access) system by using an array of SSFBGs(superstructured fiber Bragg gratings). The feasibility of the system is shown by the simulations. The Q-factor for the system was 14.53 dB when the well-known Gold codes are used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.17-17
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• 2001

본 논문은 0.6㎛ CMOS 기술로 LZSS 알고리즘과 엔트로피 부호를 이용한 부호기/복호기 단일-칩의 본 논문은 0.6uul CMOS 기술로 LZSS 알고리즘과 엔트로피 부호를 이용한 부호기/복호기 단일-칩의 VLSI 설계 및 구현에 관하여 기술하였다. 처리 속도 50MHz를 갖는 사전탐색처리장치(DISP)의 메모리는 2K×Bbit 크기를 사용하였다. 이것은 매번 33개 클럭 중 한 개의 클럭은 사전의 WINDOW 배열을 갱신으로 사용하고 나머지 클럭은 주기마다 한 개의 데이터 기호를 바이트 단위로 압축을 실행한다. 결과적으로, LZSS 부호어 출력에 엔트로피 부호를 적용하여 46%의 평균 압축률을 보였다. 이것은 LZSS에 보다 7% 정도의 압축 성능이 향상된 것이다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.181-183
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• 2004

본 논문은 패킷 방식의 OFDM(orthogonal frequency division multiplexing) 시스템에서 등화기 출력과 비터비 복호기 출력을 이용한 잔존 주파수 옵셋 추정 법을 제안한다 패킷 방식의 OFDM에서는 패킷의 앞 부분의 훈련열을 이용하여 한번 추정하기 때문에 시간이 지남에 따라 추정 오차에 의한 위상 회전이 축적된다. 이러한 위상 회전의 축적을 막기 위해 등화기 출력과 비터비 복호기의 출력에서 잔존 주파수 옵셋을 추정하여 매 심볼마다 보상한다. 잔존 주파수 옵셋의 추정은 먼저 첫 번째 심복의 등화기 출력과 그것의 비터비 복호기 출력 사이에서 위상차를 구한다. 두 번째 심복의 위상차도 처음 심복과 같은 방법으로 구한다. 두 번째 구한 위상차는 이전 심볼의 위상차에서 잔존 주파수 옵셋의 영향이 더해져 있다. 이득 두개의 위상차의 차로부터 잔존 주과수 옵셋을 구할 수 있다. 이 방법은 전송된 데이터를 사용하여 추정하기 때문에 추가적인 훈련열을 사용하지 않고 매 심볼마다 보상을 할 수 있다는 장점이 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.725-732
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• 2002

Block-wise MAP (Maximum A posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The ER (Bit Error Rate) performance of previous block-wise MAP decoding algorithm depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the EBR performance can be maintained with shorter blocks when training length is sufficient. This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding schema for reducing memory by using the training length, which in N times larger than block length. To efficiently handle the proposed schema, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.434-440
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• 2003

Since Jacquine introduced the image coding algorithm using fractal theory, many fractal image compression algorithms providing good quality at low bit rate have been proposed by Fisher and Beaumount et al.. But a problem of the previous implementations is that the decoding rests on an iterative procedure whose complexity is image-dependent. This paper proposes an iterative-free fractal image decoding algorithm to reduce the decoding time. In the proposed method, under the encoder previously with the same codebook image as an initial image to be used at the decoder, the fractal coefficients are obtained through calculating the similarity between the codebook image and an input image to be encoded. As the decoding process can be completed with received fractal coefficients and predefined initial image without repeated iterations, the decoding time could be remarkably reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8A
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• pp.821-828
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• 2008

In this paper, we present an optimized design of RS(23,17) decoder for UWB, which uses the pipeline structured-modified Euclidean(PS-ME) algorithm. Firstly, the modified processing element(PE) block is presented in order to get rid of degree comparison circuits, registers and MUX at the final PE stage. Also, a degree computationless decoding algorithm is proposed, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. Additionally, we optimize Chien search algorithm, Forney algorithm, and FIFO size for UWB specification. Using Verilog HDL, the proposed decoder is implemented and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 17,628.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.737-745
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• 1999

In this paper, we present encoders and decoders with the two kinds of ternary Bose-Chaudhuri-Hocquenghem(BCH) codes in the most basic ternary code system from among multiple-valued code systems. One is the random-triple-error-correcting ternary BCH(26,14) code for sequential data, the other is random-triple -error-correcting ternary BCH (26,13) code. The encoders and the decoders realized are verified by experiment. Amount of the (26,13) decoder's hardware is about 50% of the one of the (26,14) decoder's one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.533-536
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• 2005

MAP algorithm is known for optimal decoding algorithm of Turbo codes, but it has very large computational complexity and delay. Generally log-MAP algorithm is used in order to overcome the defect. In this paper we propose modified scheme of the state metric calculation block which can improve the computation speed in log-MAP decoder and simple linear offset unit without using LUT. The simulation results show that the operation speed of the proposed scheme is improved as compared with that of the past scheme.