• Journal of the Korea Society of Computer and Information
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• v.15 no.12
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• pp.93-100
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• 2010

In this paper, we propose a technique which makes it faster to delete prefixes in an IP address lookup architecture based on parallel TCAMs. In previous deletion schemes, more than one memory movement is needed for the prefix ordering and keeping the available memory space consecutive. For deletion, our scheme stores the address of the deleted prefix in a stack implemented by SRAM instead of actual movement in TCAM. Since SRAM has very short latency compared to TCAM, the proposed scheme can accomplish fast updating. From the experiment with the real forwarding table and update trace, we evaluate the performance of our scheme in terms of the memory access time for the prefix insertion and deletion. The experiment result also shows good performance with considerably small size of stack.

• The Journal of the Korea Contents Association
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• v.13 no.2
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• pp.44-51
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• 2013

Routers should perform fast IP address lookup for Internet to provide high-speed service. In this paper, we present a hybrid parallel IP address lookup structure composed of four-stage pipeline. It achieves parallelism at low cost by using multiple SRAMs in stage 2 and partitioned TCAMs in stage 3, and improves the performance through pipelining. The smart distributor in stage 1 does not transfer any IP address identical to previous one toward the next stage, but only uses the result of the previous lookup. So it improves throughput of lookup by caching effects, and decreases the access conflict to TCAM bank in stage 3 as well. In the last stage, the reorder buffer rearranges the completed IP addresses according to the input order. We evaluate the performance of our parallel pipelined IP lookup structure comparing with previous hybrid structure, using the real routing table and traffic distributions generated by Zipf's law.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2B
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• pp.158-166
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• 2004

Address lookup is one of the most essential functions of the Internet routers and a very important feature in evaluating router performance. Due to the facts that the Internet traffic keeps growing and the number of routing table entries is continuously growing, efficient address-lookup mechanism is indispensable. In recent years, various fast address-lookup schemes have been proposed, but most of those schemes are not practical in terms of the memory size required for routing table and the complexity required in table update In this paper, we have proposed a parallel IP address lookup architecture based on multiple hashing. The proposed scheme has advantages in required memory size, the number of memory accesses, and table update. We have evaluated the performance of the proposed scheme through simulation using data from MAE-WEST router. The simulation result shows that the proposed scheme requires a single memory access for the address lookup of each route when 203kbytes of memory and a few-hundred-entry TCAM are used.