• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.3-11
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• 2013

Recently, a plenty of researches have been conducted using the massively parallel processing of GPU for the implementation of communication system. In this paper, we tried to reduce software simulation time applying GPU with sliding block method to Viterbi decoder in DVB-T system which is one of European DTV standards. First of all, we implement DVB-T system by CPU and estimate cost time whereby the system processes one OFDM symbol. Secondly, we implement Viterbi decoder by software using NVIDIA's massive GPU processor. In our work, stream process method is applied to reduce the overhead for data transfer between CPU and GPU, as well as coalescing method to lower the global memory access time. In addition, data structure design method is used to maximize the shared memory usage. Consequently, our proposed method is approximately 11 times faster in 2K mode and 60 times faster in 8K mode for the process in Viterbi decoder.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.12
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• pp.469-478
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• 2017

The mutual exclusion is originally based on the theory of race condition prevention in symmetric multi-processor operating systems. But recently, due to the generalization of multi-core processors, its application range has been rapidly shifted to parallel processing application domain. POSIX thread, WIN32 thread, and Java thread, which are typical parallel processing application development environments, provide a unique mutual exclusion mechanism for each of them. Applications that are very sensitive to performance in these environments may want to reduce the burden of mutual exclusion, even at some cost, such as inconvenience of coding. In this study, we implement Dekker's and Peterson's algorithm in the form of busy-wait and processor-yield in various platforms, and compare the performance of them with the built-in mutual exclusion mechanisms to evaluate the usability of the classic algorithms. The analysis result shows that Dekker's algorithm of processor-yield type is superior to the built-in mechanisms in POSIX and WIN32 thread environments at least 2 times and up to 70 times, and confirms that the practicality of the algorithm is sufficient.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.26-36
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• 2000

A circularly polarized $12\times12$ array with application in the satellite communications is designed at 10 GHz. The radiator is an aperture-coupled ring patch, which is suitable of large arrays. The element spacing of the array is chosen to be $0.7\lambda_0$to maintain the main beam in the broadside direction. The array is a sequential array constructed on a series-parallel feed network to obtain high gain and low axial ratio. Measurement results for the array, acquired by experiments in the compact range of POSTECH, showed a directivity of 27.88 dB, a high gain of 25.55 dB, an efficiency of 60%, an axial ratio of 1.74 dB, and a side-lobe level of -13 dB. The bandwidth of the array was 43% when the VSWR was 2, and the bandwidth of the axial ratio was 16%.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1591-1592
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• 2006

이동 및 정보통신 시스템이 소형화 및 고성능화됨에 따라 System OR Package (SOP) 기술의 연구개발이 주목을 받고 있다. 저가형 SOP를 위하여 가장 많은 연구가 다층인쇄회로 기판에 수동소자 및 전송선로를 내장시키는 것이다. 본 논문에서는, 8층 KB 기판에 Meander line과 Radial/T Stub 패턴을 Advanced Design System(ADS) simulation을 이용하여 설계 및 제작하고 분석함으로써 정확한 SOP 디자인 및 설계 방향을 제시하고자 한다. 설계변수-패턴의 length, width, spacing, 각도와 공정변수-1층/3층, 기판 재질(prepreg(PP)과 resin coated copper(RCC))을 두어 제작하여 그 특성을 비교하였다. Meander Line는 PP보다 RCC에서의 인덕턴스가 크고 높은 자가 공진주파수를 가졌고, 3층보다 1층에서의 인덕턴스가 안정적이었다. Radial/T Stub는 PP보다 RCC에서의 커패시턴스가 작으나, 높은 자가 공진 주파수로 커패시턴스가 안정적이었다. Meander Line은 RCC, 병렬 전송선로 간격-400um, 병렬 전송선로 길이-500um, 1층 설계 시, 인덕턴스-1.60nH, 자가 공진주파수-9.21GHz 특성이 가장 우수하고, Radial Stub는 RCC, $60^{\circ}$, 1층 설계 시, 커패시턴스-0.62pF, 자가 공진주파수-9.06GHz의 특성이 나타났고, T Stub는 RCC, Stub 길이-600um, Stub 너비-150um, 1층 설계 시, 커패시턴스 -0.38pF, 자가 공진주파수-10GHz이상으로 우수한 특성을 나타냈다.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.469-478
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• 2001

It is difficult to test a distributed system because of the task of controlling concurrent events,. Existing works do not propose the test sequence generation algorithm in a formal way and the amount of message is large due to synchronization. In this paper, we propose a formal test sequence generation algorithm using logical clock to control concurrent events. It can solve the control-observation problem and makes the test results reproducible. It also provides a generic solution such that the algorithm can be used for any possible communication paradigm. In distributed test, the number of channels among the testers increases non-linearly with the number of distributed objects. We propose a new remote test architecture for solving this problem. SDL Tool is used to verify the correctness of the proposed algorithm and it is applied to the message exchange for the establishment of Q.2971 point-to-multipoint call/connection as a case study.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.335-346
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• 2004

PtolemyII is an environment that supports heterogeneous modeling and design of concurrent systems such as embedded system. PtolemyII has several Domains which are physical rules to determine the way of communicating between components. PtolemyII has 11 domains such as PetriNet, Timed Multitasking, SR etc. Components of System can be specified using appropriate domains for their properties. Communicating Sequential Processes(CSP) is implemented as formally designed CSP domain, in PtolemyII. But CCS didn't be implemented as a domain. It is a kind of Process Algebra language which can be used for specifying and verifying concurrent systems formally. Thus, in this paper we implemented CCS domain. And that permitted developers using PtolemyII to use the same modeling pattern used in PtolemyII and to make system specifications in the base of the formal semantics of CCS. This caused the diversity of PtolemyII domains and the power of expression was improved. This paper will explain the structure of CCS domain implemented in PtolemyII and the way of implementing it.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.1
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• pp.113-119
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• 2004

Exponentiation is widely used in practical applications related with cryptography, and as the discrete log is easily solved in case of a low exponent n, a large exponent n is needed for a more secure system. However. since the time complexity for exponentiation algorithm increases in proportion to the n figure, the development of an exponentiation algorithm that can quickly process the results is becoming a crucial problem. In this paper, we propose a parallel exponentiation algorithm which can reduce the number of rounds with a fixed number of processors, where the field elements are in GF($2^m$), and also analyzed the round bound of the proposed algorithm. The proposed method uses window method which divides the exponent in a particular bit length and make idle processors in window value computation phase to multiply some terms of windows where the values are already computed. By this way. the proposed method has improved round bound.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.481-496
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• 2021

It is imperative to migrate the current public key cryptosystem to a quantum-resistance system ahead of the realization of large-scale quantum computing technology. The National Institute of Standards and Technology, NIST, is promoting a public standardization project for Post-Quantum Cryptography(PQC) and also many research efforts have been conducted to apply PQC to TLS(Transport Layer Security) protocols, which are used for Internet communication security. In this paper, we propose a scenario in which a server and multi-clients share session keys on TLS by using the parallelized NTRU which is PQC in the key exchange process. In addition, we propose a method of accelerating NTRU using GPU and analyze its efficiency in an environment where a server needs to process large-scale data simultaneously.

• Journal of Internet Computing and Services
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• v.6 no.6
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• pp.23-34
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• 2005

In a large scale parallel computation, failures of some nodes or communication links end up with waste of computing resources, Several fault-tolerant MPI libraries have been proposed so far, but the programs written by using such libraries have a portability problem since fault-tolerant features are not supported by the MPI standard yet, In this paper, we propose an application-level fault-tolerant linear system solver that uses the asynchronous iteration algorithm and the standard MPI functions only, which does not have a portability problem and is more efficient by adopting a simplified recovery mechanism.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.5
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• pp.15-20
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• 2012

In this paper, we show new method to find the error locations of received Reed-Solomon code word. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square/$X^4$ calculating circuit, parallel processing and not using the very complex Divider. The Reed Solomon decoder using this new Chien Machine can be applicated for data protection of almost all digital communication and consumer electronic devices.